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https://github.com/c64scene-ar/llvm-6502.git
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Initial X86 codegen support for VSETCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
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51b2b9e29e
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@ -530,6 +530,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::VSETCC, (MVT::ValueType)VT, Expand);
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}
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if (Subtarget->hasMMX()) {
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@ -614,6 +615,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
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setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
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setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
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}
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if (Subtarget->hasSSE2()) {
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@ -639,6 +641,12 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
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setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
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setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
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setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
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setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
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setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
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setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
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@ -686,6 +694,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
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}
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if (Subtarget->hasSSE41()) {
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@ -565,7 +565,6 @@ namespace llvm {
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MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
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MachineBasicBlock *BB,
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unsigned cmovOpc);
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};
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}
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@ -161,6 +161,22 @@ def PSxLDQ_imm : SDNodeXForm<imm, [{
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return getI32Imm(N->getValue() >> 3);
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}]>;
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def SSE_CC_imm : SDNodeXForm<cond, [{
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unsigned Val;
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switch (N->get()) {
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default: Val = 0; assert(0 && "Unexpected CondCode"); break;
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case ISD::SETOEQ: Val = 0; break;
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case ISD::SETOLT: Val = 1; break;
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case ISD::SETOLE: Val = 2; break;
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case ISD::SETUO: Val = 3; break;
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case ISD::SETONE: Val = 4; break;
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case ISD::SETOGE: Val = 5; break;
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case ISD::SETOGT: Val = 6; break;
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case ISD::SETO: Val = 7; break;
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}
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return getI8Imm(Val);
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}]>;
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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@ -255,6 +271,7 @@ def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isSHUFPMask(N);
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}], SHUFFLE_get_shuf_imm>;
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//===----------------------------------------------------------------------===//
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// SSE scalar FP Instructions
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//===----------------------------------------------------------------------===//
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@ -855,16 +872,20 @@ let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
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VR128:$src, imm:$cc))]>;
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
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VR128:$src, imm:$cc))]>;
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def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
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(load addr:$src), imm:$cc))]>;
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(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
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(load addr:$src), imm:$cc))]>;
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}
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def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
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(CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
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(CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
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// Shuffle and unpack instructions
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let Constraints = "$src1 = $dst" in {
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@ -1675,13 +1696,17 @@ let Constraints = "$src1 = $dst" in {
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
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"cmp${cc}pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
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VR128:$src, imm:$cc))]>;
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VR128:$src, imm:$cc))]>;
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def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
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"cmp${cc}pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
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(load addr:$src), imm:$cc))]>;
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(load addr:$src), imm:$cc))]>;
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}
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def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
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// Shuffle and unpack instructions
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let Constraints = "$src1 = $dst" in {
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