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Revert 147426 because it caused pr11696.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13139,24 +13139,6 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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// The VSELECT instruction is lowered to SSE blend instructions. In many cases
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// the mask is sign-extended to fill the entire lane. However, we only care
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// for the highest bit. Convert sign_extend to srl because it is cheaper.
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// (vselect(sign_extend(x))) -> vselect(srl(x))
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if (N->getOpcode() == ISD::VSELECT &&
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Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) {
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EVT CondVT = Cond.getValueType();
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EVT SExtTy = cast<VTSDNode>(Cond.getOperand(1))->getVT();
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unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() -
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SExtTy.getScalarType().getSizeInBits();
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EVT ShiftType = EVT::getVectorVT(*DAG.getContext(),
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MVT::i32, CondVT.getVectorNumElements());
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SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0),
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DAG.getConstant(BitsDiff, ShiftType));
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return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS);
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}
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return SDValue();
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}
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@ -5,10 +5,8 @@ target triple = "x86_64-apple-darwin11.2.0"
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; CHECK: @foo8
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; CHECK: psll
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; CHECK-NOT: sra
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; CHECK: pandn
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; CHECK: pand
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; CHECK: or
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; CHECK: psraw
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; CHECK: pblendvb
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; CHECK: ret
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define void @foo8(float* nocapture %RET) nounwind {
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allocas:
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@ -1,15 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s
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; CHECK: foo
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define <4 x double> @foo(<4 x double> %x, <4 x double> %y) {
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; CHECK: cmpnlepd
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; CHECK: psllq
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; CHECK-NEXT: blendvpd
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; CHECK: psllq
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; CHECK-NEXT: blendvpd
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; CHECK: ret
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%min_is_x = fcmp ult <4 x double> %x, %y
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%min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y
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ret <4 x double> %min
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}
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@ -28,10 +28,10 @@ define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK: vsel_i64
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; CHECK: pxor
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; CHECK: and
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; CHECK: andn
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; CHECK: or
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; CHECK: xorps
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; CHECK: andps
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
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@ -44,10 +44,10 @@ define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
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; Without forcing instructions, fall back to the preferred PS domain.
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; CHECK: vsel_double
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; CHECK: xor
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; CHECK: and
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; CHECK: andn
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; CHECK: or
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; CHECK: xorps
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; CHECK: andps
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; CHECK: andnps
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; CHECK: orps
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; CHECK: ret
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define void@vsel_double(<4 x double>* %v1, <4 x double>* %v2) {
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@ -36,7 +36,6 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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;CHECK: vsel_double
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;CHECK-NOT: sra
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;CHECK: blendvpd
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;CHECK: ret
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define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
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@ -55,7 +54,6 @@ define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
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;CHECK: vsel_i8
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;CHECK-NOT: sra
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;CHECK: pblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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@ -67,7 +65,6 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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; CHECK: A
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define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmplepd
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; CHECK-NOT: sra
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; CHECK: blendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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@ -77,7 +74,6 @@ define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
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; CHECK: B
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define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmpnlepd
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; CHECK-NOT: sra
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; CHECK: blendvpd
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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