mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-17 20:29:31 +00:00
* Simplify code a bit by breaking the PHI node handling stuff out into a seperate
function from normal regalloc code * Make the regalloc for a block a function instead of part of runOnMachineBB, which makes it easier to see what's going on in runOnMBB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
afe628c1d6
commit
c2db1a95df
@ -60,10 +60,8 @@ namespace {
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std::map<unsigned, unsigned> RegsUsed;
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std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
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RegAllocSimple(TargetMachine &tm) : TM(tm),
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RegInfo(tm.getRegisterInfo()),
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PhysRegClasses(RegInfo)
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{
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RegAllocSimple(TargetMachine &tm)
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: TM(tm), RegInfo(tm.getRegisterInfo()), PhysRegClasses(RegInfo) {
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RegsUsed[RegInfo->getFramePointer()] = 1;
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RegsUsed[RegInfo->getStackPointer()] = 1;
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@ -75,7 +73,8 @@ namespace {
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return RegsUsed.find(Reg) == RegsUsed.end();
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}
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///
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/// allocateStackSpaceFor - This allocates space for the specified virtual
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/// register to be held on the stack.
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unsigned allocateStackSpaceFor(unsigned VirtReg,
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const TargetRegisterClass *regClass);
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@ -85,7 +84,7 @@ namespace {
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/// Returns all `borrowed' registers back to the free pool
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void clearAllRegs() {
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RegClassIdx.clear();
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RegClassIdx.clear();
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}
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/// Invalidates any references, real or implicit, to physical registers
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@ -106,23 +105,23 @@ namespace {
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void cleanupAfterFunction() {
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VirtReg2OffsetMap.clear();
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SSA2PhysRegMap.clear();
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NumBytesAllocated = 4; /* FIXME: This is X86 specific */
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NumBytesAllocated = 4; // FIXME: This is X86 specific
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}
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/// Moves value from memory into that register
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MachineBasicBlock::iterator
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moveUseToReg (MachineBasicBlock *MBB,
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moveUseToReg (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned VirtReg,
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unsigned &PhysReg);
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/// Saves reg value on the stack (maps virtual register to stack value)
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MachineBasicBlock::iterator
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saveVirtRegToStack (MachineBasicBlock *MBB,
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saveVirtRegToStack (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned VirtReg,
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unsigned PhysReg);
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MachineBasicBlock::iterator
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savePhysRegToStack (MachineBasicBlock *MBB,
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savePhysRegToStack (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned PhysReg);
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/// runOnFunction - Top level implementation of instruction selection for
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@ -130,6 +129,13 @@ namespace {
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///
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bool runOnMachineFunction(MachineFunction &Fn);
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/// AllocateBasicBlock - Register allocate the specified basic block.
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
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/// in predecessor basic blocks.
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void EliminatePHINodes(MachineBasicBlock &MBB);
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bool runOnFunction(Function &Fn) {
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return runOnMachineFunction(MachineFunction::get(&Fn));
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}
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@ -137,6 +143,8 @@ namespace {
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}
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/// allocateStackSpaceFor - This allocates space for the specified virtual
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/// register to be held on the stack.
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unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg,
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const TargetRegisterClass *regClass)
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{
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@ -180,7 +188,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
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}
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MachineBasicBlock::iterator
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RegAllocSimple::moveUseToReg (MachineBasicBlock *MBB,
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RegAllocSimple::moveUseToReg (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned &PhysReg)
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{
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@ -191,13 +199,13 @@ RegAllocSimple::moveUseToReg (MachineBasicBlock *MBB,
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PhysReg = getFreeReg(VirtReg);
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// Add move instruction(s)
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return RegInfo->loadRegOffset2Reg(MBB, I, PhysReg,
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return RegInfo->loadRegOffset2Reg(&MBB, I, PhysReg,
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RegInfo->getFramePointer(),
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-stackOffset, regClass->getDataSize());
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}
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MachineBasicBlock::iterator
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RegAllocSimple::saveVirtRegToStack (MachineBasicBlock *MBB,
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RegAllocSimple::saveVirtRegToStack (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg)
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{
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@ -207,13 +215,13 @@ RegAllocSimple::saveVirtRegToStack (MachineBasicBlock *MBB,
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unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass);
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// Add move instruction(s)
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return RegInfo->storeReg2RegOffset(MBB, I, PhysReg,
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return RegInfo->storeReg2RegOffset(&MBB, I, PhysReg,
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RegInfo->getFramePointer(),
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-stackOffset, regClass->getDataSize());
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}
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MachineBasicBlock::iterator
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RegAllocSimple::savePhysRegToStack (MachineBasicBlock *MBB,
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RegAllocSimple::savePhysRegToStack (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned PhysReg)
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{
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@ -223,157 +231,157 @@ RegAllocSimple::savePhysRegToStack (MachineBasicBlock *MBB,
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unsigned offset = allocateStackSpaceFor(PhysReg, regClass);
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// Add move instruction(s)
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return RegInfo->storeReg2RegOffset(MBB, I, PhysReg,
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return RegInfo->storeReg2RegOffset(&MBB, I, PhysReg,
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RegInfo->getFramePointer(),
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offset, regClass->getDataSize());
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}
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bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
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cleanupAfterFunction();
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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/// predecessor basic blocks.
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void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) {
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while (MBB.front()->getOpcode() == 0) {
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MachineInstr *MI = MBB.front();
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// get rid of the phi
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MBB.erase(MBB.begin());
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// a preliminary pass that will invalidate any registers that
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// are used by the instruction (including implicit uses)
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invalidatePhysRegs(MI);
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DEBUG(std::cerr << "num invalid regs: " << RegsUsed.size() << "\n");
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DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n");
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MachineOperand &targetReg = MI->getOperand(0);
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// If it's a virtual register, allocate a physical one
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// otherwise, just use whatever register is there now
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// note: it MUST be a register -- we're assigning to it
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unsigned virtualReg = (unsigned) targetReg.getAllocatedRegNum();
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unsigned physReg;
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if (targetReg.isVirtualRegister()) {
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physReg = getFreeReg(virtualReg);
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} else {
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physReg = virtualReg;
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}
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// Find the register class of the target register: should be the
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// same as the values we're trying to store there
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const TargetRegisterClass* regClass = PhysRegClasses[physReg];
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assert(regClass && "Target register class not found!");
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unsigned dataSize = regClass->getDataSize();
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for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
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MachineOperand &opVal = MI->getOperand(i-1);
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the
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// source path the phi
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MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
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MachineBasicBlock::iterator opI = opBlock.end();
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MachineInstr *opMI = *--opI;
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const MachineInstrInfo &MII = TM.getInstrInfo();
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unsigned virtualReg, physReg;
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// must backtrack over ALL the branches in the previous block, until no
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// more
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while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
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opMI = *--opI;
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// move back to the first branch instruction so new instructions
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// are inserted right in front of it and not in front of a non-branch
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if (!MII.isBranch(opMI->getOpcode()))
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++opI;
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// Retrieve the constant value from this op, move it to target
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// register of the phi
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if (opVal.isImmediate()) {
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opI = RegInfo->moveImm2Reg(&opBlock, opI, physReg,
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(unsigned) opVal.getImmedValue(),
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dataSize);
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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} else {
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// Allocate a physical register and add a move in the BB
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unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum();
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unsigned opPhysReg; // = getFreeReg(opVirtualReg);
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opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg);
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//opI = RegInfo->moveReg2Reg(opBlock, opI, physReg, opPhysReg,
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// dataSize);
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// Save that register value to the stack of the TARGET REG
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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}
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// make regs available to other instructions
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clearAllRegs();
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}
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// really delete the instruction
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delete MI;
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}
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}
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void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Handle PHI instructions specially: add moves to each pred block
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EliminatePHINodes(MBB);
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//loop over each basic block
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
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MachineInstr *MI = *I;
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// a preliminary pass that will invalidate any registers that
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// are used by the instruction (including implicit uses)
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invalidatePhysRegs(MI);
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// Loop over uses, move from memory into registers
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &op = MI->getOperand(i);
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if (op.isImmediate()) {
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DEBUG(std::cerr << "const\n");
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} else if (op.isVirtualRegister()) {
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unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
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DEBUG(std::cerr << "op: " << op << "\n");
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DEBUG(std::cerr << "\t inst[" << i << "]: ";
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MI->print(std::cerr, TM));
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// make sure the same virtual register maps to the same physical
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// register in any given instruction
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unsigned physReg;
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if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) {
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physReg = VirtReg2PhysRegMap[virtualReg];
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} else {
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if (op.opIsDef()) {
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if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
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// must be same register number as the first operand
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// This maps a = b + c into b += c, and saves b into a's spot
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physReg = (unsigned) MI->getOperand(1).getAllocatedRegNum();
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} else {
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physReg = getFreeReg(virtualReg);
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}
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MachineBasicBlock::iterator J = I;
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J = saveVirtRegToStack(MBB, ++J, virtualReg, physReg);
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I = --J;
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} else {
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I = moveUseToReg(MBB, I, virtualReg, physReg);
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}
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VirtReg2PhysRegMap[virtualReg] = physReg;
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}
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MI->SetMachineOperandReg(i, physReg);
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DEBUG(std::cerr << "virt: " << virtualReg <<
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", phys: " << op.getAllocatedRegNum() << "\n");
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}
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}
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clearAllRegs();
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VirtReg2PhysRegMap.clear();
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}
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}
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bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
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DEBUG(std::cerr << "Machine Function " << "\n");
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MF = &Fn;
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB)
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{
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MachineBasicBlock *CurrMBB = &(*MBB);
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// Handle PHI instructions specially: add moves to each pred block
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while (MBB->front()->getOpcode() == 0) {
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MachineInstr *MI = MBB->front();
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// get rid of the phi
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MBB->erase(MBB->begin());
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// a preliminary pass that will invalidate any registers that
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// are used by the instruction (including implicit uses)
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invalidatePhysRegs(MI);
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DEBUG(std::cerr << "num invalid regs: " << RegsUsed.size() << "\n");
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DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n");
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MachineOperand &targetReg = MI->getOperand(0);
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// If it's a virtual register, allocate a physical one
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// otherwise, just use whatever register is there now
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// note: it MUST be a register -- we're assigning to it
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virtualReg = (unsigned) targetReg.getAllocatedRegNum();
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if (targetReg.isVirtualRegister()) {
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physReg = getFreeReg(virtualReg);
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} else {
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physReg = virtualReg;
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}
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// Find the register class of the target register: should be the
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// same as the values we're trying to store there
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const TargetRegisterClass* regClass = PhysRegClasses[physReg];
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assert(regClass && "Target register class not found!");
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unsigned dataSize = regClass->getDataSize();
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for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
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MachineOperand &opVal = MI->getOperand(i-1);
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the
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// source path the phi
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MachineBasicBlock *opBlock = MI->getOperand(i).getMachineBasicBlock();
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MachineBasicBlock::iterator opI = opBlock->end();
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MachineInstr *opMI = *(--opI);
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const MachineInstrInfo &MII = TM.getInstrInfo();
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// must backtrack over ALL the branches in the previous block, until no more
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while ((MII.isBranch(opMI->getOpcode()) || MII.isReturn(opMI->getOpcode()))
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&& opI != opBlock->begin())
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{
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opMI = *(--opI);
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}
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// move back to the first branch instruction so new instructions
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// are inserted right in front of it and not in front of a non-branch
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++opI;
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// Retrieve the constant value from this op, move it to target
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// register of the phi
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if (opVal.getType() == MachineOperand::MO_SignExtendedImmed ||
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opVal.getType() == MachineOperand::MO_UnextendedImmed)
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{
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opI = RegInfo->moveImm2Reg(opBlock, opI, physReg,
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(unsigned) opVal.getImmedValue(),
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dataSize);
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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} else {
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// Allocate a physical register and add a move in the BB
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unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum();
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unsigned opPhysReg; // = getFreeReg(opVirtualReg);
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opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg);
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//opI = RegInfo->moveReg2Reg(opBlock, opI, physReg, opPhysReg,
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// dataSize);
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// Save that register value to the stack of the TARGET REG
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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}
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// make regs available to other instructions
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clearAllRegs();
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}
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// really delete the instruction
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delete MI;
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}
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//loop over each basic block
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for (MachineBasicBlock::iterator I = MBB->begin(); I != MBB->end(); ++I)
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{
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MachineInstr *MI = *I;
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// a preliminary pass that will invalidate any registers that
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// are used by the instruction (including implicit uses)
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invalidatePhysRegs(MI);
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// Loop over uses, move from memory into registers
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &op = MI->getOperand(i);
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if (op.getType() == MachineOperand::MO_SignExtendedImmed ||
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op.getType() == MachineOperand::MO_UnextendedImmed)
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{
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DEBUG(std::cerr << "const\n");
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} else if (op.isVirtualRegister()) {
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virtualReg = (unsigned) op.getAllocatedRegNum();
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DEBUG(std::cerr << "op: " << op << "\n");
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DEBUG(std::cerr << "\t inst[" << i << "]: ";
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MI->print(std::cerr, TM));
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// make sure the same virtual register maps to the same physical
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// register in any given instruction
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if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) {
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physReg = VirtReg2PhysRegMap[virtualReg];
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} else {
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if (op.opIsDef()) {
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if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
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// must be same register number as the first operand
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// This maps a = b + c into b += c, and saves b into a's spot
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physReg = (unsigned) MI->getOperand(1).getAllocatedRegNum();
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} else {
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physReg = getFreeReg(virtualReg);
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}
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MachineBasicBlock::iterator J = I;
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J = saveVirtRegToStack(CurrMBB, ++J, virtualReg, physReg);
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I = --J;
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} else {
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I = moveUseToReg(CurrMBB, I, virtualReg, physReg);
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}
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VirtReg2PhysRegMap[virtualReg] = physReg;
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}
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MI->SetMachineOperandReg(i, physReg);
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DEBUG(std::cerr << "virt: " << virtualReg <<
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", phys: " << op.getAllocatedRegNum() << "\n");
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}
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}
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clearAllRegs();
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VirtReg2PhysRegMap.clear();
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}
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}
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AllocateBasicBlock(*MBB);
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// add prologue we should preserve callee-save registers...
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MachineFunction::iterator Fi = Fn.begin();
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@ -381,21 +389,22 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
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MachineBasicBlock::iterator MBBi = MBB->begin();
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RegInfo->emitPrologue(MBB, MBBi, NumBytesAllocated);
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const MachineInstrInfo &MII = TM.getInstrInfo();
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// add epilogue to restore the callee-save registers
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// loop over the basic block
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB)
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{
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MBB != MBBe; ++MBB) {
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// check if last instruction is a RET
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MachineBasicBlock::iterator I = (*MBB).end();
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MachineInstr *MI = *(--I);
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const MachineInstrInfo &MII = TM.getInstrInfo();
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MachineBasicBlock::iterator I = MBB->end();
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MachineInstr *MI = *--I;
|
||||
if (MII.isReturn(MI->getOpcode())) {
|
||||
// this block has a return instruction, add epilogue
|
||||
RegInfo->emitEpilogue(MBB, I, NumBytesAllocated);
|
||||
}
|
||||
}
|
||||
|
||||
cleanupAfterFunction();
|
||||
return false; // We never modify the LLVM itself.
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user