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ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -116,13 +116,13 @@ def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
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let ParserMatchClass = VecListFourDAsmOperand;
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}
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// Register list of two D registers spaced by 2 (two sequential Q registers).
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def VecListTwoQAsmOperand : AsmOperandClass {
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let Name = "VecListTwoQ";
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def VecListDPairSpacedAsmOperand : AsmOperandClass {
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let Name = "VecListDPairSpaced";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
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let ParserMatchClass = VecListTwoQAsmOperand;
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def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListDPairSpaced"> {
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let ParserMatchClass = VecListDPairSpacedAsmOperand;
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}
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// Register list of three D registers spaced by 2 (three Q registers).
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def VecListThreeQAsmOperand : AsmOperandClass {
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@ -803,12 +803,12 @@ def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
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def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
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// ...with double-spaced registers
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def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
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def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
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def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
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defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
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defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
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defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
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def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
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def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
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def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
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defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
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defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
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defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
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// VLD3 : Vector Load (multiple 3-element structures)
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class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -1810,12 +1810,12 @@ def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
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def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
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// ...with double-spaced registers
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def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
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def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
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def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
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defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
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defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
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defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
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def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
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def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
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def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
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defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
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defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
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defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
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// VST3 : Vector Store (multiple 3-element structures)
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class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -1106,6 +1106,12 @@ public:
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return VectorList.Count == 2;
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}
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bool isVecListDPairSpaced() const {
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if (!isSingleSpacedVectorList()) return false;
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return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
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.contains(VectorList.RegNum));
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}
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bool isVecListThreeQ() const {
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if (!isDoubleSpacedVectorList()) return false;
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return VectorList.Count == 3;
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@ -2974,9 +2980,6 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (LaneKind) {
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case NoLanes:
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E = Parser.getTok().getLoc();
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// VLD1 wants a DPair register.
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// FIXME: Make the rest of the two-reg instructions want the same
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// thing.
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Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
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&ARMMCRegisterClasses[ARM::DPairRegClassID]);
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@ -3149,13 +3152,14 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (LaneKind) {
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case NoLanes:
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if (Count == 2 && Spacing == 1)
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// VLD1 wants a DPair register.
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// FIXME: Make the rest of the two-reg instructions want the same
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// thing.
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FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0,
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&ARMMCRegisterClasses[ARM::DPairRegClassID]);
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// Non-lane two-register operands have been converted to the
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// composite register classes.
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if (Count == 2) {
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const MCRegisterClass *RC = (Spacing == 1) ?
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&ARMMCRegisterClasses[ARM::DPairRegClassID] :
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&ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
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FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
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}
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Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
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(Spacing == 2), S, E));
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@ -128,6 +128,9 @@ static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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@ -1008,6 +1011,29 @@ static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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return MCDisassembler::Success;
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}
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static const unsigned DPairSpacedDecoderTable[] = {
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ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
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ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
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ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
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ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
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ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
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ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
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ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
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ARM::D28_D30, ARM::D29_D31
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};
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static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 29)
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return MCDisassembler::Fail;
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unsigned Register = DPairSpacedDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (Val == 0xF) return MCDisassembler::Fail;
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@ -1999,6 +2025,18 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
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if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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break;
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case ARM::VLD2b16:
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case ARM::VLD2b32:
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case ARM::VLD2b8:
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case ARM::VLD2b16wb_fixed:
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case ARM::VLD2b16wb_register:
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case ARM::VLD2b32wb_fixed:
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case ARM::VLD2b32wb_register:
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case ARM::VLD2b8wb_fixed:
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case ARM::VLD2b8wb_register:
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if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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break;
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default:
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if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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@ -2358,6 +2396,18 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
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if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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break;
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case ARM::VST2b16:
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case ARM::VST2b32:
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case ARM::VST2b8:
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case ARM::VST2b16wb_fixed:
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case ARM::VST2b16wb_register:
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case ARM::VST2b32wb_fixed:
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case ARM::VST2b32wb_register:
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case ARM::VST2b8wb_fixed:
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case ARM::VST2b8wb_register:
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if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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break;
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default:
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if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
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return MCDisassembler::Fail;
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@ -1042,6 +1042,15 @@ void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum,
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O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
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}
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void ARMInstPrinter::printVectorListDPairSpaced(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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unsigned Reg = MI->getOperand(OpNum).getReg();
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unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
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unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
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O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
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}
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void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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@ -135,6 +135,8 @@ public:
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void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorListDPair(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorListDPairSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
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@ -574,11 +574,10 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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REG("QQPR");
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REG("QQQQPR");
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REG("VecListOneD");
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REG("VecListTwoD");
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REG("VecListDPair");
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REG("VecListDPairSpaced");
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REG("VecListThreeD");
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REG("VecListFourD");
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REG("VecListTwoQ");
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REG("VecListOneDAllLanes");
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REG("VecListTwoDAllLanes");
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REG("VecListTwoQAllLanes");
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