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Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-16 20:56:08 +00:00
parent 75604f81b7
commit c3a289c4b5
2 changed files with 18 additions and 14 deletions
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24
lib/CodeGen/IfConversion.cpp
View File

@ -68,7 +68,7 @@ namespace {
std::vector<int> &Candidates);
bool IfConvertDiamond(BBInfo &BBI);
bool IfConvertTriangle(BBInfo &BBI);
bool isBlockPredicatable(MachineBasicBlock *BB,
bool isBlockPredicable(MachineBasicBlock *BB,
bool IgnoreTerm = false) const;
void PredicateBlock(MachineBasicBlock *BB,
std::vector<MachineOperand> &Cond,
@ -190,7 +190,7 @@ void IfConverter::InitialFunctionAnalysis(MachineFunction &MF,
}
bool IfConverter::IfConvertTriangle(BBInfo &BBI) {
if (isBlockPredicatable(BBI.TBB, true)) {
if (isBlockPredicable(BBI.TBB, true)) {
// Predicate the 'true' block after removing its branch.
TII->RemoveBranch(*BBI.TBB);
PredicateBlock(BBI.TBB, BBI.Cond);
@ -214,28 +214,28 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI) {
}
bool IfConverter::IfConvertDiamond(BBInfo &BBI) {
if (isBlockPredicatable(BBI.TBB, true) &&
isBlockPredicatable(BBI.FBB, true)) {
if (isBlockPredicable(BBI.TBB, true) &&
isBlockPredicable(BBI.FBB, true)) {
std::vector<MachineInstr*> Dups;
if (!BBI.CMBB) {
// No common merge block. Check if the terminators (e.g. return) are
// the same or predicatable.
// the same or predicable.
MachineBasicBlock::iterator TT = BBI.TBB->getFirstTerminator();
MachineBasicBlock::iterator FT = BBI.FBB->getFirstTerminator();
while (TT != BBI.TBB->end() && FT != BBI.FBB->end()) {
if (TT->isIdenticalTo(FT))
Dups.push_back(TT); // Will erase these later.
else if (!TII->isPredicatable(TT) && !TII->isPredicatable(FT))
else if (!TT->isPredicable() && !FT->isPredicable())
return false; // Can't if-convert. Abort!
++TT;
++FT;
}
while (TT != BBI.TBB->end())
if (!TII->isPredicatable(TT))
if (!TT->isPredicable())
return false; // Can't if-convert. Abort!
while (FT != BBI.FBB->end())
if (!TII->isPredicatable(FT))
if (!FT->isPredicable())
return false; // Can't if-convert. Abort!
}
@ -270,17 +270,17 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI) {
return false;
}
/// isBlockPredicatable - Returns true if the block is predicatable. In most
/// cases, that means all the instructions in the block has M_PREDICATED flag.
/// isBlockPredicable - Returns true if the block is predicable. In most
/// cases, that means all the instructions in the block has M_PREDICABLE flag.
/// If IgnoreTerm is true, assume all the terminator instructions can be
/// converted or deleted.
bool IfConverter::isBlockPredicatable(MachineBasicBlock *BB,
bool IfConverter::isBlockPredicable(MachineBasicBlock *BB,
bool IgnoreTerm) const {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
I != E; ++I) {
if (IgnoreTerm && TII->isTerminatorInstr(I->getOpcode()))
continue;
if (!TII->isPredicatable(I))
if (!I->isPredicable())
return false;
}
return true;

8
lib/CodeGen/MachineInstr.cpp
View File

@ -184,6 +184,10 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
}
}
bool MachineInstr::isPredicable() const {
return TID->Flags & M_PREDICABLE;
}
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
@ -212,7 +216,7 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
// is used to represent the predicate.
MachineOperand *MachineInstr::findFirstPredOperand() {
const TargetInstrDescriptor *TID = getInstrDescriptor();
if (TID->Flags & M_PREDICATED) {
if (TID->Flags & M_PREDICABLE) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
return &getOperand(i);
@ -244,7 +248,7 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_PREDICATED) {
if (TID->Flags & M_PREDICABLE) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
const MachineOperand &MO = MI->getOperand(i);