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Remove the -live-regunits command line option.

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Register allocators depend on it being permanently enabled now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158873 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-06-20 23:31:34 +00:00
parent 12a7be9ba4
commit c4118452bc
2 changed files with 4 additions and 13 deletions
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16
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -27,7 +27,6 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@ -40,9 +39,6 @@
#include <cmath>
using namespace llvm;
// Temporary option to enable regunit liveness.
static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden, cl::init(true));
STATISTIC(numIntervals , "Number of original intervals");
char LiveIntervals::ID = 0;
@ -62,8 +58,7 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveVariables>();
AU.addPreserved<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
if (LiveRegUnits)
AU.addRequiredTransitiveID(MachineDominatorsID);
AU.addRequiredTransitiveID(MachineDominatorsID);
AU.addPreservedID(MachineDominatorsID);
AU.addPreserved<SlotIndexes>();
AU.addRequiredTransitive<SlotIndexes>();
@ -109,9 +104,8 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
AA = &getAnalysis<AliasAnalysis>();
LV = &getAnalysis<LiveVariables>();
Indexes = &getAnalysis<SlotIndexes>();
if (LiveRegUnits)
DomTree = &getAnalysis<MachineDominatorTree>();
if (LiveRegUnits && !LRCalc)
DomTree = &getAnalysis<MachineDominatorTree>();
if (!LRCalc)
LRCalc = new LiveRangeCalc();
AllocatableRegs = TRI->getAllocatableSet(fn);
ReservedRegs = TRI->getReservedRegs(fn);
@ -120,9 +114,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
numIntervals += getNumIntervals();
if (LiveRegUnits) {
computeLiveInRegUnits();
}
computeLiveInRegUnits();
DEBUG(dump());
return true;

1
test/CodeGen/X86/misched-new.ll
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@ -1,5 +1,4 @@
; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s
; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup -live-regunits < %s
; REQUIRES: asserts
;
; Interesting MachineScheduler cases.