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Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-10-12 04:46:18 +00:00
parent 7f0125ba19
commit c429b5cca1
2 changed files with 19 additions and 21 deletions
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36
lib/Target/X86/X86InstrSSE.td
View File

@ -1114,15 +1114,15 @@ let isCodeGenOnly = 1 in {
"movapd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (alignedloadfsf64 addr:$src))],
IIC_SSE_MOVA_P_RM>, VEX;
def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
"movaps\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (alignedloadfsf32 addr:$src))],
IIC_SSE_MOVA_P_RM>;
def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
"movapd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (alignedloadfsf64 addr:$src))],
IIC_SSE_MOVA_P_RM>;
}
def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
"movaps\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (alignedloadfsf32 addr:$src))],
IIC_SSE_MOVA_P_RM>;
def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
"movapd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (alignedloadfsf64 addr:$src))],
IIC_SSE_MOVA_P_RM>;
}
//===----------------------------------------------------------------------===//
@ -2840,16 +2840,18 @@ multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
}
// Alias bitwise logical operations using SSE logical ops on packed FP values.
defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
SSE_BIT_ITINS_P>;
defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
SSE_BIT_ITINS_P>;
defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
SSE_BIT_ITINS_P>;
let isCommutable = 0 in
defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
let isCodeGenOnly = 1 in {
defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
SSE_BIT_ITINS_P>;
defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
SSE_BIT_ITINS_P>;
defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
SSE_BIT_ITINS_P>;
let isCommutable = 0 in
defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
SSE_BIT_ITINS_P>;
}
/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
///

4
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -529,10 +529,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
// Special cases.
if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
return FILTER_WEAK;
if (Name.find("Fs") != Name.npos)
return FILTER_WEAK;
if (Name == "PUSH64i16" ||
Name == "MOVPQI2QImr" ||
Name == "VMOVPQI2QImr" ||