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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Fill in more omissions in DebugLog propagation.
I think that's it for this directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63690 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1108,7 +1108,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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unsigned Reg = TLI.getExceptionAddressRegister();
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Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
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Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
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}
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break;
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case TargetLowering::Custom:
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@ -1142,7 +1142,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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unsigned Reg = TLI.getExceptionSelectorRegister();
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Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
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Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
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}
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break;
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case TargetLowering::Custom:
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@ -1911,7 +1911,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
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SDValue Size = Tmp2.getOperand(1);
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SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
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Chain = SP.getValue(1);
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unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
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unsigned StackAlign =
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@ -1920,7 +1920,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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SP = DAG.getNode(ISD::AND, dl, VT, SP,
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DAG.getConstant(-(uint64_t)Align, VT));
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
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Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
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Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
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Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
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DAG.getIntPtrConstant(0, true), SDValue());
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@ -2882,7 +2882,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// Expand to CopyFromReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
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Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
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Node->getValueType(0));
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Tmp2 = Tmp1.getValue(1);
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} else {
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@ -2914,7 +2914,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// Expand to CopyToReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
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Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
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} else {
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Result = Tmp1;
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}
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@ -4029,7 +4029,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Result = PromoteOp(Node->getOperand(0));
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// For FP, make Op1 a i32
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Result = DAG.getConvertRndSat(Op.getValueType(), Result,
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Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
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DTyOp, STyOp, RndOp, SatOp, CvtCode);
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break;
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}
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@ -4593,7 +4593,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
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CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
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"can only promote integers");
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Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
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Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
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Node->getOperand(1), Node->getOperand(2),
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Node->getOperand(3), Node->getOperand(4),
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CvtCode);
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@ -4877,11 +4877,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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Tmp1 = Node->getOperand(0); // Get the chain.
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Tmp2 = Node->getOperand(1); // Get the pointer.
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if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
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Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
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Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
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Result = TLI.LowerOperation(Tmp3, DAG);
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} else {
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const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
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SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
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// Increment the pointer, VAList, to the next vaarg
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Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
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DAG.getConstant(VT.getSizeInBits()/8,
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@ -6578,8 +6578,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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case ISD::VAARG: {
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SDValue Ch = Node->getOperand(0); // Legalize the chain.
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SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
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Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
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Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
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Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
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Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
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// Remember that we legalized the chain.
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Hi = LegalizeOp(Hi);
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@ -7744,9 +7744,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue RndOp = Node->getOperand(3);
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SDValue SatOp = Node->getOperand(4);
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Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
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Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
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RndOp, SatOp, CvtCode);
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Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
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Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
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RndOp, SatOp, CvtCode);
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break;
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}
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@ -7892,7 +7892,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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break;
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case ISD::CONVERT_RNDSAT: {
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SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
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Result = DAG.getConvertRndSat(NewVT, Op0,
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Result = DAG.getConvertRndSat(NewVT, dl, Op0,
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DAG.getValueType(NewVT),
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DAG.getValueType(Op0.getValueType()),
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Node->getOperand(3),
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@ -8199,7 +8199,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
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SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
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ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
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Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
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Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
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RndOp, SatOp, CvtCode);
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break;
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}
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@ -262,7 +262,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
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CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
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"can only promote integers");
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MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
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return DAG.getConvertRndSat(OutVT, N->getOperand(0),
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return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
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N->getOperand(1), N->getOperand(2),
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N->getOperand(3), N->getOperand(4), CvtCode);
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}
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@ -608,7 +608,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
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SmallVector<SDValue, 8> Parts(NumRegs);
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for (unsigned i = 0; i < NumRegs; ++i) {
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Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
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Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
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Chain = Parts[i].getValue(1);
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}
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@ -823,7 +823,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
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CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
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"can only promote integer arguments");
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SDValue InOp = GetPromotedInteger(N->getOperand(0));
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return DAG.getConvertRndSat(N->getValueType(0), InOp,
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return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
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N->getOperand(1), N->getOperand(2),
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N->getOperand(3), N->getOperand(4), CvtCode);
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}
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@ -209,9 +209,10 @@ void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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SDValue Chain = N->getOperand(0);
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SDValue Ptr = N->getOperand(1);
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DebugLoc dl = N->getDebugLoc();
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Lo = DAG.getVAArg(NVT, Chain, Ptr, N->getOperand(2));
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Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, N->getOperand(2));
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Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
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Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2));
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// Handle endianness of the load.
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if (TLI.isBigEndian())
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@ -126,7 +126,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
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SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
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MVT NewVT = N->getValueType(0).getVectorElementType();
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SDValue Op0 = GetScalarizedVector(N->getOperand(0));
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return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
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return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
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Op0, DAG.getValueType(NewVT),
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DAG.getValueType(Op0.getValueType()),
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N->getOperand(3),
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N->getOperand(4),
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@ -533,6 +534,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
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void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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MVT LoVT, HiVT;
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DebugLoc dl = N->getDebugLoc();
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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SDValue VLo, VHi;
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GetSplitVector(N->getOperand(0), VLo, VHi);
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@ -545,8 +547,10 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
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SDValue SatOp = N->getOperand(4);
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ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
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Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
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Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
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Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
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CvtCode);
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Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
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CvtCode);
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}
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void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
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@ -1454,6 +1458,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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SDValue InOp = N->getOperand(0);
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SDValue RndOp = N->getOperand(3);
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SDValue SatOp = N->getOperand(4);
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@ -1475,7 +1480,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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InVT = InOp.getValueType();
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InVTNumElts = InVT.getVectorNumElements();
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if (InVTNumElts == WidenNumElts)
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return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
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return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
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SatOp, CvtCode);
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}
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@ -1490,20 +1495,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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unsigned NumConcat = WidenNumElts/InVTNumElts;
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SmallVector<SDValue, 16> Ops(NumConcat);
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Ops[0] = InOp;
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
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for (unsigned i = 1; i != NumConcat; ++i) {
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Ops[i] = UndefVal;
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}
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InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat);
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return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
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InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
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return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
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SatOp, CvtCode);
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}
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if (InVTNumElts % WidenNumElts == 0) {
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// Extract the input and convert the shorten input vector.
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InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp,
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InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
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DAG.getIntPtrConstant(0));
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return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
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return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
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SatOp, CvtCode);
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}
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}
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@ -1517,17 +1522,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
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unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
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unsigned i;
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for (i=0; i < MinElts; ++i) {
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SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
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SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
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DAG.getIntPtrConstant(i));
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Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp,
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Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
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SatOp, CvtCode);
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}
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
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SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
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for (; i < WidenNumElts; ++i)
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Ops[i] = UndefVal;
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return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
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return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
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}
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SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
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@ -440,9 +440,11 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
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MVT VT = Arg.getValueType();
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unsigned VReg = MF.getRegInfo().
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createVirtualRegister(TLI.getRegClassFor(VT));
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Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
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Chain = DAG.getCopyToReg(Chain, Arg.getNode()->getDebugLoc(),
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VReg, Arg, InFlag);
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InFlag = Chain.getValue(1);
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Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
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Arg = DAG.getCopyFromReg(Chain, Arg.getNode()->getDebugLoc(),
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VReg, VT, InFlag);
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Chain = Arg.getValue(1);
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InFlag = Arg.getValue(2);
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}
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