mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-08 09:43:20 +00:00
Temporarily workaround JM/lencod miscompile (SIGSEGV).
rdar://problem/8893967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
bd1801b555
commit
c48d50f9c0
@ -1645,11 +1645,13 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
|
||||
// NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
|
||||
// counts data deps. To be more precise, we could maintain a
|
||||
// NumDataSuccsLeft count.
|
||||
/* FIXME: exposing a downstream bug, JM/lencode miscompile
|
||||
if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
|
||||
DEBUG(dbgs() << " SU(" << PredSU->NodeNum << ") live across SU("
|
||||
<< SU->NodeNum << ")\n");
|
||||
continue;
|
||||
}
|
||||
*/
|
||||
const SDNode *PN = PredSU->getNode();
|
||||
if (!PN->isMachineOpcode()) {
|
||||
if (PN->getOpcode() == ISD::CopyFromReg) {
|
||||
|
Loading…
x
Reference in New Issue
Block a user