6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-20 11:32:33 +00:00
Code Issues Projects Releases Wiki Activity

Removed unused argument.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-09-03 03:16:09 +00:00
parent 8a04e51d86
commit c4d2560a20
5 changed files with 20 additions and 24 deletions
include/llvm/MC
MCTargetAsmParser.h
lib/Target
ARM/AsmParser
ARMAsmParser.cpp
MBlaze/AsmParser
MBlazeAsmParser.cpp
X86/AsmParser
X86AsmParser.cpp
utils/TableGen
AsmMatcherEmitter.cpp

2
include/llvm/MC/MCTargetAsmParser.h

@ -85,7 +85,7 @@ public:
/// On failure, the target parser is responsible for emitting a diagnostic
/// explaining the match failure.
virtual bool
MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
MatchInstruction(SMLoc IDLoc, unsigned &Kind,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts,
unsigned &OrigErrorInfo,

3
lib/Target/ARM/AsmParser/ARMAsmParser.cpp

@ -7457,11 +7457,10 @@ MatchAndEmitInstruction(SMLoc IDLoc,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
unsigned MatchResult;
MatchResult = MatchInstructionImpl(Operands, Kind, Opcode, Inst, ErrorInfo);
MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo);
switch (MatchResult) {
default: break;
case Match_Success:

3
lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp

@ -318,10 +318,9 @@ MatchAndEmitInstruction(SMLoc IDLoc,
MCStreamer &Out) {
MCInst Inst;
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
switch (MatchInstructionImpl(Operands, Kind, Opcode, Inst, ErrorInfo)) {
switch (MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo)) {
default: break;
case Match_Success:
Out.EmitInstruction(Inst);

27
lib/Target/X86/AsmParser/X86AsmParser.cpp

@ -67,7 +67,7 @@ private:
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out);
bool MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
bool MatchInstruction(SMLoc IDLoc, unsigned &Kind,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts,
unsigned &OrigErrorInfo,
@ -1517,11 +1517,10 @@ MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
SmallVector<MCInst, 2> Insts;
bool Error = MatchInstruction(IDLoc, Kind, Opcode, Operands, Insts,
bool Error = MatchInstruction(IDLoc, Kind, Operands, Insts,
ErrorInfo);
if (!Error)
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
@ -1530,7 +1529,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
}
bool X86AsmParser::
MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
MatchInstruction(SMLoc IDLoc, unsigned &Kind,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SmallVectorImpl<MCInst> &MCInsts, unsigned &OrigErrorInfo,
bool matchingInlineAsm) {
@ -1572,7 +1571,7 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
MCInst Inst;
// First, try a direct match.
switch (MatchInstructionImpl(Operands, Kind, Opcode, Inst, OrigErrorInfo,
switch (MatchInstructionImpl(Operands, Kind, Inst, OrigErrorInfo,
isParsingIntelSyntax())) {
default: break;
case Match_Success:
@ -1620,19 +1619,19 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned &Opcode,
Tmp[Base.size()] = Suffixes[0];
unsigned ErrorInfoIgnore;
unsigned Match1, Match2, Match3, Match4;
unsigned tKind, tOpcode;
unsigned tKind;
Match1 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match1 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Match1 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore);
if (Match1 == Match_Success) Kind = tKind;
Tmp[Base.size()] = Suffixes[1];
Match2 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match2 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Match2 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore);
if (Match2 == Match_Success) Kind = tKind;
Tmp[Base.size()] = Suffixes[2];
Match3 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match3 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Match3 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore);
if (Match3 == Match_Success) Kind = tKind;
Tmp[Base.size()] = Suffixes[3];
Match4 = MatchInstructionImpl(Operands, tKind, tOpcode, Inst, ErrorInfoIgnore);
if (Match4 == Match_Success) { Kind = tKind; Opcode = tOpcode; }
Match4 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore);
if (Match4 == Match_Success) Kind = tKind;
// Restore the old token.
Op->setTokenValue(Base);

9
utils/TableGen/AsmMatcherEmitter.cpp

@ -2587,8 +2587,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
OS << " unsigned MatchInstructionImpl(\n"
<< " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
<< " unsigned &Kind, unsigned &Opcode, MCInst &Inst, "
<< "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n";
<< " unsigned &Kind, MCInst &Inst, "
<< "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n";
if (Info.OperandMatchInfo.size()) {
OS << "\n enum OperandMatchResultTy {\n";
@ -2768,8 +2768,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< Target.getName() << ClassName << "::\n"
<< "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
<< " &Operands,\n";
OS << " unsigned &Kind, unsigned &Opcode, MCInst &Inst,";
OS << "\n unsigned &ErrorInfo, unsigned VariantID) {\n";
OS << " unsigned &Kind, MCInst &Inst, unsigned ";
OS << "&ErrorInfo,\n unsigned VariantID) {\n";
OS << " // Eliminate obvious mismatches.\n";
OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
@ -2887,7 +2887,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " " << InsnCleanupFn << "(Inst);\n";
OS << " Kind = it->ConvertFn;\n";
OS << " Opcode = it->Opcode;\n";
OS << " return Match_Success;\n";
OS << " }\n\n";