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https://github.com/c64scene-ar/llvm-6502.git
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Make MachineOperand's value named 'contents'. Make really, really sure
it is always completely initialized and copied. Also, fix up many comments and asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12100 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
parent
ba2e09891a
commit
c54839573c
@ -110,71 +110,80 @@ public:
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private:
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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// LLVM global for MO_GlobalAddress.
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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// LLVM global for MO_GlobalAddress.
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int immedVal; // Constant value for an explicit constant
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
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std::string *SymbolName; // For MO_ExternalSymbol type
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};
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} contents;
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char flags; // see bit field definitions above
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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private:
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void zeroContents () {
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memset (&contents, 0, sizeof (contents));
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}
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MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
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: immedVal(ImmVal),
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flags(0),
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opType(OpTy),
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regNum(-1) {}
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: flags(0), opType(OpTy), regNum(-1) {
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zeroContents ();
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}
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MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
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: immedVal(0), flags(UseTy), opType(OpTy), regNum(Reg) { }
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: flags(UseTy), opType(OpTy), regNum(Reg) {
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zeroContents ();
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}
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MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
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bool isPCRelative = false)
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: value(V),
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flags(UseTy | (isPCRelative ? PCRELATIVE : 0)),
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opType(OpTy),
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regNum(-1) {
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: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy), regNum(-1) {
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zeroContents ();
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contents.value = V;
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}
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MachineOperand(MachineBasicBlock *mbb)
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: MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) { }
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: flags(0), opType(MO_MachineBasicBlock), regNum(-1) {
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zeroContents ();
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contents.MBB = mbb;
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}
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MachineOperand(const std::string &SymName, bool isPCRelative)
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: SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
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opType(MO_ExternalSymbol), regNum(-1) {}
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: flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol), regNum(-1) {
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zeroContents ();
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contents.SymbolName = new std::string (SymName);
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}
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public:
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MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
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flags(M.flags),
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opType(M.opType),
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regNum(M.regNum) {
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MachineOperand(const MachineOperand &M)
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: flags(M.flags), opType(M.opType), regNum(M.regNum) {
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zeroContents ();
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contents = M.contents;
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if (isExternalSymbol())
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SymbolName = new std::string(M.getSymbolName());
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contents.SymbolName = new std::string(M.getSymbolName());
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}
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~MachineOperand() {
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if (isExternalSymbol())
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delete SymbolName;
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delete contents.SymbolName;
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}
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const MachineOperand &operator=(const MachineOperand &MO) {
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if (isExternalSymbol()) // if old operand had a symbol name,
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delete SymbolName; // release old memory
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immedVal = MO.immedVal;
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delete contents.SymbolName; // release old memory
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contents = MO.contents;
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flags = MO.flags;
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opType = MO.opType;
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regNum = MO.regNum;
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if (isExternalSymbol())
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SymbolName = new std::string(MO.getSymbolName());
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contents.SymbolName = new std::string(MO.getSymbolName());
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return *this;
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}
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@ -184,9 +193,7 @@ public:
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/// getUseType - Returns the MachineOperandUseType of this operand.
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///
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UseType getUseType() const {
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return UseType(flags & (USEFLAG|DEFFLAG));
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}
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UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); }
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/// isPCRelative - This returns the value of the PCRELATIVE flag, which
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/// indicates whether this operand should be emitted as a PC relative value
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@ -205,6 +212,8 @@ public:
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return opType == MO_MachineRegister || opType == MO_VirtualRegister;
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}
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/// Accessors that tell you what kind of MachineOperand you're looking at.
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///
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
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bool isImmediate() const {
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@ -215,83 +224,109 @@ public:
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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Value* getVRegValue() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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isPCRelativeDisp());
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return value;
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}
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/// getVRegValueOrNull - Get the Value* out of a MachineOperand if it
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/// has one. This is deprecated and only used by the SPARC v9 backend.
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///
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Value* getVRegValueOrNull() const {
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return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
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isPCRelativeDisp()) ? value : NULL;
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isPCRelativeDisp()) ? contents.value : NULL;
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}
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/// MachineOperand accessors that only work on certain types of
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/// MachineOperand...
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///
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Value* getVRegValue() const {
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assert ((opType == MO_VirtualRegister || opType == MO_CCRegister
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|| isPCRelativeDisp()) && "Wrong MachineOperand accessor");
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return contents.value;
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}
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int getMachineRegNum() const {
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assert(opType == MO_MachineRegister);
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assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor");
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return regNum;
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}
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int getImmedValue() const { assert(isImmediate()); return immedVal; }
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void setImmedValue(int ImmVal) { assert(isImmediate()); immedVal = ImmVal; }
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int getImmedValue() const {
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assert(isImmediate() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
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return MBB;
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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int getFrameIndex() const {
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assert(isFrameIndex() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
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unsigned getConstantPoolIndex() const {
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assert(isConstantPoolIndex());
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return immedVal;
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assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
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return contents.immedVal;
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}
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GlobalValue *getGlobal() const {
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assert(isGlobalAddress());
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return (GlobalValue*)value;
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assert(isGlobalAddress() && "Wrong MachineOperand accessor");
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return (GlobalValue*)contents.value;
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}
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const std::string &getSymbolName() const {
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assert(isExternalSymbol());
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return *SymbolName;
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assert(isExternalSymbol() && "Wrong MachineOperand accessor");
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return *contents.SymbolName;
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}
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/// MachineOperand methods for testing that work on any kind of
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/// MachineOperand...
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///
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bool isUse () const { return flags & USEFLAG; }
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MachineOperand& setUse () { flags |= USEFLAG; return *this; }
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bool isDef () const { return flags & DEFFLAG; }
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bool isDef () const { return flags & DEFFLAG; }
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MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
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bool isHiBits32 () const { return flags & HIFLAG32; }
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bool isLoBits32 () const { return flags & LOFLAG32; }
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bool isHiBits64 () const { return flags & HIFLAG64; }
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bool isLoBits64 () const { return flags & LOFLAG64; }
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// used to check if a machine register has been allocated to this operand
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/// hasAllocatedReg - Returns true iff a machine register has been
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/// allocated to this operand.
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///
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bool hasAllocatedReg() const {
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return (regNum >= 0 &&
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(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister));
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}
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// used to get the reg number if when one is allocated
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/// getReg - Returns the register number. It is a runtime error to call this
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/// if a register is not allocated.
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///
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unsigned getReg() const {
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assert(hasAllocatedReg());
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return regNum;
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}
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// ********** TODO: get rid of this duplicate code! ***********
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/// MachineOperand mutators...
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///
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void setReg(unsigned Reg) {
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// This method's comment used to say: 'TODO: get rid of this duplicate
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// code.' It's not clear where the duplication is.
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assert(hasAllocatedReg() && "This operand cannot have a register number!");
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regNum = Reg;
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}
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void setImmedValue(int immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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}
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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private:
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// Construction methods needed for fine-grain control.
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// These must be accessed via coresponding methods in MachineInstr.
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/// markHi32, markLo32, etc. - These methods must be accessed via
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/// corresponding methods in MachineInstr. These methods are deprecated
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/// and only used by the SPARC v9 back-end.
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///
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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// Replaces the Value with its corresponding physical register after
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// register allocation is complete
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/// setRegForValue - Replaces the Value with its corresponding physical
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/// register after register allocation is complete. This is deprecated
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/// and only used by the SPARC v9 back-end.
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///
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void setRegForValue(int reg) {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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@ -321,18 +356,18 @@ private:
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//===----------------------------------------------------------------------===//
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class MachineInstr {
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short Opcode; // the opcode
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short Opcode; // the opcode
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unsigned char numImplicitRefs; // number of implicit operands
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std::vector<MachineOperand> operands; // the operands
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MachineInstr* prev, *next; // links for our intrusive list
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MachineBasicBlock* parent; // pointer to the owning basic block
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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private:
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// Intrusive list support
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//
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friend class ilist_traits<MachineInstr>;
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@ -358,7 +393,7 @@ public:
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const MachineBasicBlock* getParent() const { return parent; }
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MachineBasicBlock* getParent() { return parent; }
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/// Accessors for opcode.
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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const int getOpcode() const { return Opcode; }
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@ -100,7 +100,7 @@ void MachineInstr::SetMachineOperandVal(unsigned i,
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Value* V) {
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assert(i < operands.size()); // may be explicit or implicit op
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operands[i].opType = opTy;
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operands[i].value = V;
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operands[i].contents.value = V;
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operands[i].regNum = -1;
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}
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@ -113,8 +113,8 @@ MachineInstr::SetMachineOperandConst(unsigned i,
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"immed. constant cannot be defined");
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operands[i].opType = opTy;
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operands[i].value = NULL;
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operands[i].immedVal = intValue;
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operands[i].contents.value = NULL;
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operands[i].contents.immedVal = intValue;
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operands[i].regNum = -1;
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operands[i].flags = 0;
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}
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@ -123,7 +123,7 @@ void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
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assert(i < getNumOperands()); // must be explicit op
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operands[i].opType = MachineOperand::MO_MachineRegister;
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operands[i].value = NULL;
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operands[i].contents.value = NULL;
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operands[i].regNum = regNum;
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}
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@ -162,7 +162,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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notDefsAndUses && (O.isDef() && !O.isUse()) ||
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!notDefsAndUses && O.isDef())
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{
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O.getMachineOperand().value = newVal;
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O.getMachineOperand().contents.value = newVal;
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++numSubst;
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}
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else
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@ -175,7 +175,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
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!notDefsAndUses && getImplicitOp(i).isDef())
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{
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getImplicitOp(i).value = newVal;
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getImplicitOp(i).contents.value = newVal;
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++numSubst;
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}
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else
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