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variadic instructions don't have operand info for variadic arguments.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48208 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2008-03-11 03:14:42 +00:00
parent 43ca31e3dc
commit c5733ac5d3
1 changed files with 2 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@@ -538,6 +538,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// the regclass is ok.
const TargetRegisterClass *RC =
getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
assert((RC || II->isVariadic()) && "Expected reg class info!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (RC && VRC != RC) {
cerr << "Register class of operand and regclass of use don't agree!\n";
@@ -604,7 +605,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// to be able to handle it. This handles things like copies from ST(0) to
// an FP vreg on x86.
assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
if (II && !II->isVariadic()) {
assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
"Don't have operand info for this instruction!");
}