mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
Use TSFlag bit to describe instruction properties.
Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150078 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brendon Cahoon
parent
3fd3a840c5
commit
c635ebdb1a
@ -7,23 +7,37 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
// Hexagon Intruction Flags +
|
||||
//
|
||||
// *** Must match HexagonBaseInfo.h ***
|
||||
//----------------------------------------------------------------------------//
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
// Intruction Class Declaration +
|
||||
//----------------------------------------------------------------------------//
|
||||
|
||||
class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
string cstr,
|
||||
InstrItinClass itin> : Instruction {
|
||||
string cstr, InstrItinClass itin> : Instruction {
|
||||
field bits<32> Inst;
|
||||
|
||||
let Namespace = "Hexagon";
|
||||
|
||||
/* Commented out for Hexagon
|
||||
bits<2> op;
|
||||
let Inst{31-30} = op; */ // Top two bits are the 'op' field
|
||||
|
||||
dag OutOperandList = outs;
|
||||
dag InOperandList = ins;
|
||||
let AsmString = asmstr;
|
||||
let Pattern = pattern;
|
||||
let Constraints = cstr;
|
||||
let Itinerary = itin;
|
||||
|
||||
// *** The code below must match HexagonBaseInfo.h ***
|
||||
|
||||
// Predicated instructions.
|
||||
bits<1> isPredicated = 0;
|
||||
let TSFlags{1} = isPredicated;
|
||||
|
||||
// *** The code above must match HexagonBaseInfo.h ***
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
|
||||
@ -861,213 +861,9 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
|
||||
|
||||
|
||||
bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
|
||||
switch (MI->getOpcode()) {
|
||||
case Hexagon::TFR_cPt:
|
||||
case Hexagon::TFR_cNotPt:
|
||||
case Hexagon::TFRI_cPt:
|
||||
case Hexagon::TFRI_cNotPt:
|
||||
case Hexagon::TFR_cdnPt:
|
||||
case Hexagon::TFR_cdnNotPt:
|
||||
case Hexagon::TFRI_cdnPt:
|
||||
case Hexagon::TFRI_cdnNotPt:
|
||||
return true;
|
||||
const uint64_t F = MI->getDesc().TSFlags;
|
||||
|
||||
case Hexagon::JMP_Pred:
|
||||
case Hexagon::JMP_PredNot:
|
||||
case Hexagon::BRCOND:
|
||||
case Hexagon::JMP_PredPt:
|
||||
case Hexagon::JMP_PredNotPt:
|
||||
case Hexagon::JMP_PredPnt:
|
||||
case Hexagon::JMP_PredNotPnt:
|
||||
return true;
|
||||
|
||||
case Hexagon::LDrid_indexed_cPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
|
||||
return true;
|
||||
|
||||
case Hexagon::LDrid_cPt :
|
||||
case Hexagon::LDrid_cNotPt :
|
||||
case Hexagon::LDrid_indexed_cPt :
|
||||
case Hexagon::LDrid_indexed_cNotPt :
|
||||
case Hexagon::POST_LDrid_cPt :
|
||||
case Hexagon::POST_LDrid_cNotPt :
|
||||
case Hexagon::LDriw_cPt :
|
||||
case Hexagon::LDriw_cNotPt :
|
||||
case Hexagon::LDriw_indexed_cPt :
|
||||
case Hexagon::LDriw_indexed_cNotPt :
|
||||
case Hexagon::POST_LDriw_cPt :
|
||||
case Hexagon::POST_LDriw_cNotPt :
|
||||
case Hexagon::LDrih_cPt :
|
||||
case Hexagon::LDrih_cNotPt :
|
||||
case Hexagon::LDrih_indexed_cPt :
|
||||
case Hexagon::LDrih_indexed_cNotPt :
|
||||
case Hexagon::POST_LDrih_cPt :
|
||||
case Hexagon::POST_LDrih_cNotPt :
|
||||
case Hexagon::LDrib_cPt :
|
||||
case Hexagon::LDrib_cNotPt :
|
||||
case Hexagon::LDrib_indexed_cPt :
|
||||
case Hexagon::LDrib_indexed_cNotPt :
|
||||
case Hexagon::POST_LDrib_cPt :
|
||||
case Hexagon::POST_LDrib_cNotPt :
|
||||
case Hexagon::LDriuh_cPt :
|
||||
case Hexagon::LDriuh_cNotPt :
|
||||
case Hexagon::LDriuh_indexed_cPt :
|
||||
case Hexagon::LDriuh_indexed_cNotPt :
|
||||
case Hexagon::POST_LDriuh_cPt :
|
||||
case Hexagon::POST_LDriuh_cNotPt :
|
||||
case Hexagon::LDriub_cPt :
|
||||
case Hexagon::LDriub_cNotPt :
|
||||
case Hexagon::LDriub_indexed_cPt :
|
||||
case Hexagon::LDriub_indexed_cNotPt :
|
||||
case Hexagon::POST_LDriub_cPt :
|
||||
case Hexagon::POST_LDriub_cNotPt :
|
||||
return true;
|
||||
|
||||
case Hexagon::LDrid_cdnPt :
|
||||
case Hexagon::LDrid_cdnNotPt :
|
||||
case Hexagon::LDrid_indexed_cdnPt :
|
||||
case Hexagon::LDrid_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrid_cdnPt_V4 :
|
||||
case Hexagon::POST_LDrid_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_cdnPt :
|
||||
case Hexagon::LDriw_cdnNotPt :
|
||||
case Hexagon::LDriw_indexed_cdnPt :
|
||||
case Hexagon::LDriw_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriw_cdnPt_V4 :
|
||||
case Hexagon::POST_LDriw_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_cdnPt :
|
||||
case Hexagon::LDrih_cdnNotPt :
|
||||
case Hexagon::LDrih_indexed_cdnPt :
|
||||
case Hexagon::LDrih_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrih_cdnPt_V4 :
|
||||
case Hexagon::POST_LDrih_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_cdnPt :
|
||||
case Hexagon::LDrib_cdnNotPt :
|
||||
case Hexagon::LDrib_indexed_cdnPt :
|
||||
case Hexagon::LDrib_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDrib_cdnPt_V4 :
|
||||
case Hexagon::POST_LDrib_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_cdnPt :
|
||||
case Hexagon::LDriuh_cdnNotPt :
|
||||
case Hexagon::LDriuh_indexed_cdnPt :
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriuh_cdnPt_V4 :
|
||||
case Hexagon::POST_LDriuh_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_cdnPt :
|
||||
case Hexagon::LDriub_cdnNotPt :
|
||||
case Hexagon::LDriub_indexed_cdnPt :
|
||||
case Hexagon::LDriub_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriub_cdnPt_V4 :
|
||||
case Hexagon::POST_LDriub_cdnNotPt_V4 :
|
||||
return true;
|
||||
|
||||
case Hexagon::ADD_ri_cPt:
|
||||
case Hexagon::ADD_ri_cNotPt:
|
||||
case Hexagon::ADD_ri_cdnPt:
|
||||
case Hexagon::ADD_ri_cdnNotPt:
|
||||
case Hexagon::ADD_rr_cPt:
|
||||
case Hexagon::ADD_rr_cNotPt:
|
||||
case Hexagon::ADD_rr_cdnPt:
|
||||
case Hexagon::ADD_rr_cdnNotPt:
|
||||
case Hexagon::XOR_rr_cPt:
|
||||
case Hexagon::XOR_rr_cNotPt:
|
||||
case Hexagon::XOR_rr_cdnPt:
|
||||
case Hexagon::XOR_rr_cdnNotPt:
|
||||
case Hexagon::AND_rr_cPt:
|
||||
case Hexagon::AND_rr_cNotPt:
|
||||
case Hexagon::AND_rr_cdnPt:
|
||||
case Hexagon::AND_rr_cdnNotPt:
|
||||
case Hexagon::OR_rr_cPt:
|
||||
case Hexagon::OR_rr_cNotPt:
|
||||
case Hexagon::OR_rr_cdnPt:
|
||||
case Hexagon::OR_rr_cdnNotPt:
|
||||
case Hexagon::SUB_rr_cPt:
|
||||
case Hexagon::SUB_rr_cNotPt:
|
||||
case Hexagon::SUB_rr_cdnPt:
|
||||
case Hexagon::SUB_rr_cdnNotPt:
|
||||
case Hexagon::COMBINE_rr_cPt:
|
||||
case Hexagon::COMBINE_rr_cNotPt:
|
||||
case Hexagon::COMBINE_rr_cdnPt:
|
||||
case Hexagon::COMBINE_rr_cdnNotPt:
|
||||
return true;
|
||||
|
||||
case Hexagon::ASLH_cPt_V4:
|
||||
case Hexagon::ASLH_cNotPt_V4:
|
||||
case Hexagon::ASRH_cPt_V4:
|
||||
case Hexagon::ASRH_cNotPt_V4:
|
||||
case Hexagon::SXTB_cPt_V4:
|
||||
case Hexagon::SXTB_cNotPt_V4:
|
||||
case Hexagon::SXTH_cPt_V4:
|
||||
case Hexagon::SXTH_cNotPt_V4:
|
||||
case Hexagon::ZXTB_cPt_V4:
|
||||
case Hexagon::ZXTB_cNotPt_V4:
|
||||
case Hexagon::ZXTH_cPt_V4:
|
||||
case Hexagon::ZXTH_cNotPt_V4:
|
||||
return true;
|
||||
|
||||
case Hexagon::ASLH_cdnPt_V4:
|
||||
case Hexagon::ASLH_cdnNotPt_V4:
|
||||
case Hexagon::ASRH_cdnPt_V4:
|
||||
case Hexagon::ASRH_cdnNotPt_V4:
|
||||
case Hexagon::SXTB_cdnPt_V4:
|
||||
case Hexagon::SXTB_cdnNotPt_V4:
|
||||
case Hexagon::SXTH_cdnPt_V4:
|
||||
case Hexagon::SXTH_cdnNotPt_V4:
|
||||
case Hexagon::ZXTB_cdnPt_V4:
|
||||
case Hexagon::ZXTB_cdnNotPt_V4:
|
||||
case Hexagon::ZXTH_cdnPt_V4:
|
||||
case Hexagon::ZXTH_cdnNotPt_V4:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#ifndef HexagonINSTRUCTIONINFO_H
|
||||
#define HexagonINSTRUCTIONINFO_H
|
||||
|
||||
#include "MCTargetDesc/HexagonBaseInfo.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetFrameLowering.h"
|
||||
#include "HexagonRegisterInfo.h"
|
||||
|
||||
@ -319,49 +319,49 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Conditional add.
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
|
||||
"if ($src1) $dst = add($src2, #$src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
|
||||
"if (!$src1) $dst = add($src2, #$src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
|
||||
"if ($src1.new) $dst = add($src2, #$src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
|
||||
"if (!$src1.new) $dst = add($src2, #$src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = add($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = add($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = add($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = add($src2, $src3)",
|
||||
@ -370,25 +370,25 @@ def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
|
||||
// Conditional combine.
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = combine($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = combine($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = combine($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = combine($src2, $src3)",
|
||||
@ -396,61 +396,73 @@ def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
|
||||
|
||||
// Conditional logical operations.
|
||||
|
||||
let isPredicated = 1 in
|
||||
def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = xor($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = xor($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = xor($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = xor($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = and($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = and($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = and($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = and($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = or($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = or($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = or($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = or($src2, $src3)",
|
||||
@ -459,21 +471,25 @@ def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
|
||||
// Conditional subtract.
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = sub($src2, $src3)",
|
||||
@ -482,47 +498,47 @@ def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
|
||||
// Conditional transfer.
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = $src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
"if (!$src1) $dst = $src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2),
|
||||
"if ($src1) $dst = #$src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
s12Imm:$src2),
|
||||
"if (!$src1) $dst = #$src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
"if ($src1.new) $dst = $src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = $src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
s12Imm:$src2),
|
||||
"if ($src1.new) $dst = #$src2",
|
||||
[]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1,
|
||||
s12Imm:$src2),
|
||||
"if (!$src1.new) $dst = #$src2",
|
||||
@ -743,7 +759,8 @@ let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
|
||||
}
|
||||
|
||||
// if (p0) jump
|
||||
let isBranch = 1, isTerminator=1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_Pred : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if ($src) jump $offset",
|
||||
@ -751,14 +768,16 @@ let isBranch = 1, isTerminator=1, Defs = [PC] in {
|
||||
}
|
||||
|
||||
// if (!p0) jump
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_PredNot : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if (!$src) jump $offset",
|
||||
[]>;
|
||||
}
|
||||
|
||||
let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
|
||||
"if ($pred) jump $dst",
|
||||
[]>;
|
||||
@ -766,7 +785,8 @@ let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
|
||||
// Jump to address conditioned on new predicate.
|
||||
// if (p0) jump:t
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_PredPt : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if ($src.new) jump:t $offset",
|
||||
@ -774,7 +794,8 @@ let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
}
|
||||
|
||||
// if (!p0) jump:t
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_PredNotPt : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if (!$src.new) jump:t $offset",
|
||||
@ -782,7 +803,8 @@ let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
}
|
||||
|
||||
// Not taken.
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_PredPnt : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if ($src.new) jump:nt $offset",
|
||||
@ -790,7 +812,8 @@ let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
}
|
||||
|
||||
// Not taken.
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
|
||||
let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
|
||||
isPredicated = 1 in {
|
||||
def JMP_PredNotPnt : JInst< (outs),
|
||||
(ins PredRegs:$src, brtarget:$offset),
|
||||
"if (!$src.new) jump:nt $offset",
|
||||
@ -1779,7 +1802,8 @@ def POST_STdri_cPt : STInstPI<(outs IntRegs:$dst),
|
||||
"$src3 = $dst">;
|
||||
|
||||
// if (!Pv) memd(Rx++#s4:3)=Rtt
|
||||
let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in
|
||||
let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STdri_cNotPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
|
||||
s4_3Imm:$offset),
|
||||
@ -1859,14 +1883,14 @@ def STrib_indexed_cNotPt : STInst<(outs),
|
||||
|
||||
// if ([!]Pv) memb(Rx++#s4:0)=Rt
|
||||
// if (Pv) memb(Rx++#s4:0)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_STbri_cPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if ($src1) memb($src3++#$offset) = $src2",
|
||||
[],"$src3 = $dst">;
|
||||
|
||||
// if (!Pv) memb(Rx++#s4:0)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_STbri_cNotPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if (!$src1) memb($src3++#$offset) = $src2",
|
||||
@ -1944,14 +1968,14 @@ def STrih_indexed_cNotPt : STInst<(outs),
|
||||
|
||||
// if ([!]Pv) memh(Rx++#s4:1)=Rt
|
||||
// if (Pv) memh(Rx++#s4:1)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_SThri_cPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if ($src1) memh($src3++#$offset) = $src2",
|
||||
[],"$src3 = $dst">;
|
||||
|
||||
// if (!Pv) memh(Rx++#s4:1)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_SThri_cNotPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if (!$src1) memh($src3++#$offset) = $src2",
|
||||
@ -2030,14 +2054,14 @@ def STriw_indexed_cNotPt : STInst<(outs),
|
||||
|
||||
// if ([!]Pv) memw(Rx++#s4:2)=Rt
|
||||
// if (Pv) memw(Rx++#s4:2)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_STwri_cPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if ($src1) memw($src3++#$offset) = $src2",
|
||||
[],"$src3 = $dst">;
|
||||
|
||||
// if (!Pv) memw(Rx++#s4:2)=Rt
|
||||
let mayStore = 1, hasCtrlDep = 1 in
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in
|
||||
def POST_STwri_cNotPt : STInstPI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if (!$src1) memw($src3++#$offset) = $src2",
|
||||
|
||||
@ -77,48 +77,56 @@
|
||||
|
||||
// Shift halfword.
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = aslh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = aslh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = aslh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = aslh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = asrh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = asrh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = asrh($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = asrh($src2)",
|
||||
@ -127,24 +135,28 @@ def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
|
||||
// Sign extend.
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = sxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = sxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = sxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = sxtb($src2)",
|
||||
@ -152,24 +164,28 @@ def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = sxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = sxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = sxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = sxth($src2)",
|
||||
@ -178,56 +194,56 @@ def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
|
||||
// Zero exten.
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = zxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = zxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = zxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = zxtb($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1) $dst = zxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1) $dst = zxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if ($src1.new) $dst = zxth($src2)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2),
|
||||
"if (!$src1.new) $dst = zxth($src2)",
|
||||
@ -276,7 +292,7 @@ def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
//// Load doubleword conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memd($src2+$src3<<#0)",
|
||||
@ -284,7 +300,7 @@ def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memd($src2+$src3<<#0)",
|
||||
@ -292,7 +308,7 @@ def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memd($src2+$src3<<#0)",
|
||||
@ -300,7 +316,7 @@ def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memd($src2+$src3<<#0)",
|
||||
@ -308,7 +324,7 @@ def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -317,7 +333,7 @@ def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -326,7 +342,7 @@ def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -335,7 +351,7 @@ def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrid_indexed_shl_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -405,7 +421,7 @@ def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
|
||||
//// Load byte conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memb($src2+$src3<<#0)",
|
||||
@ -413,7 +429,7 @@ def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memb($src2+$src3<<#0)",
|
||||
@ -421,7 +437,7 @@ def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memb($src2+$src3<<#0)",
|
||||
@ -429,7 +445,7 @@ def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memb($src2+$src3<<#0)",
|
||||
@ -437,7 +453,7 @@ def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -446,7 +462,7 @@ def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -455,7 +471,7 @@ def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -464,7 +480,7 @@ def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -475,7 +491,7 @@ def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
//// Load unsigned byte conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memub($src2+$src3<<#0)",
|
||||
@ -483,7 +499,7 @@ def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memub($src2+$src3<<#0)",
|
||||
@ -491,7 +507,7 @@ def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memub($src2+$src3<<#0)",
|
||||
@ -499,7 +515,7 @@ def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memub($src2+$src3<<#0)",
|
||||
@ -507,7 +523,7 @@ def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -516,7 +532,7 @@ def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -525,7 +541,7 @@ def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -534,7 +550,7 @@ def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriub_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -606,7 +622,7 @@ def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
|
||||
//// Load halfword conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memh($src2+$src3<<#0)",
|
||||
@ -614,7 +630,7 @@ def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memh($src2+$src3<<#0)",
|
||||
@ -622,7 +638,7 @@ def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memh($src2+$src3<<#0)",
|
||||
@ -630,7 +646,7 @@ def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memh($src2+$src3<<#0)",
|
||||
@ -638,7 +654,7 @@ def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -647,7 +663,7 @@ def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -656,7 +672,7 @@ def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -665,7 +681,7 @@ def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -676,7 +692,7 @@ def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
//// Load unsigned halfword conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memuh($src2+$src3<<#0)",
|
||||
@ -684,7 +700,7 @@ def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memuh($src2+$src3<<#0)",
|
||||
@ -692,7 +708,7 @@ def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memuh($src2+$src3<<#0)",
|
||||
@ -700,7 +716,7 @@ def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
|
||||
@ -708,7 +724,7 @@ def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -717,7 +733,7 @@ def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -726,7 +742,7 @@ def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -735,7 +751,7 @@ def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -770,7 +786,7 @@ def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
|
||||
//// Load word conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memw(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memw($src2+$src3<<#0)",
|
||||
@ -778,7 +794,7 @@ def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memw($src2+$src3<<#0)",
|
||||
@ -786,7 +802,7 @@ def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memw($src2+$src3<<#0)",
|
||||
@ -794,7 +810,7 @@ def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 15 in
|
||||
let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memw($src2+$src3<<#0)",
|
||||
@ -802,7 +818,7 @@ def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -811,7 +827,7 @@ def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -820,7 +836,7 @@ def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -829,7 +845,7 @@ def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let mayLoad = 1, AddedComplexity = 45 in
|
||||
let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in
|
||||
def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
|
||||
u2Imm:$offset),
|
||||
@ -843,7 +859,7 @@ def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),
|
||||
// Post-inc Load, Predicated, Dot new
|
||||
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memd($src2++#$src3)",
|
||||
@ -851,7 +867,7 @@ def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memd($src2++#$src3)",
|
||||
@ -859,7 +875,7 @@ def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memb($src2++#$src3)",
|
||||
@ -867,7 +883,7 @@ def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memb($src2++#$src3)",
|
||||
@ -875,7 +891,7 @@ def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memh($src2++#$src3)",
|
||||
@ -883,7 +899,7 @@ def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memh($src2++#$src3)",
|
||||
@ -891,7 +907,7 @@ def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memub($src2++#$src3)",
|
||||
@ -899,7 +915,7 @@ def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memub($src2++#$src3)",
|
||||
@ -907,7 +923,7 @@ def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memuh($src2++#$src3)",
|
||||
@ -915,7 +931,7 @@ def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memuh($src2++#$src3)",
|
||||
@ -923,7 +939,7 @@ def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
|
||||
"if ($src1.new) $dst1 = memw($src2++#$src3)",
|
||||
@ -931,7 +947,7 @@ def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
"$src2 = $dst2">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in
|
||||
let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def POST_LDriw_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3),
|
||||
"if (!$src1.new) $dst1 = memw($src2++#$src3)",
|
||||
|
||||
43
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
Normal file
43
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
Normal file
@ -0,0 +1,43 @@
|
||||
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon -------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains small standalone helper functions and enum definitions for
|
||||
// the Hexagon target useful for the compiler back-end and the MC libraries.
|
||||
// As such, it deliberately does not include references to LLVM core
|
||||
// code gen types, passes, etc..
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef HEXAGONBASEINFO_H
|
||||
#define HEXAGONBASEINFO_H
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// HexagonII - This namespace holds all of the target specific flags that
|
||||
/// instruction info tracks.
|
||||
///
|
||||
namespace HexagonII {
|
||||
|
||||
// *** The code below must match HexagonInstrFormat*.td ***
|
||||
|
||||
// MCInstrDesc TSFlags
|
||||
enum {
|
||||
|
||||
// Predicated instructions.
|
||||
PredicatedPos = 1,
|
||||
PredicatedMask = 0x1
|
||||
};
|
||||
|
||||
// *** The code above must match HexagonInstrFormat*.td ***
|
||||
|
||||
} // End namespace HexagonII.
|
||||
|
||||
} // End namespace llvm.
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user