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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
Modernize naming convention for class members.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157079 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -55,29 +55,29 @@ public:
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};
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};
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private:
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private:
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LiveInterval &parent_;
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LiveInterval &Parent;
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SmallVectorImpl<LiveInterval*> &newRegs_;
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SmallVectorImpl<LiveInterval*> &NewRegs;
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MachineRegisterInfo &MRI;
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MachineRegisterInfo &MRI;
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LiveIntervals &LIS;
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LiveIntervals &LIS;
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VirtRegMap *VRM;
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VirtRegMap *VRM;
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const TargetInstrInfo &TII;
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const TargetInstrInfo &TII;
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Delegate *const delegate_;
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Delegate *const TheDelegate;
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/// firstNew_ - Index of the first register added to newRegs_.
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/// FirstNew - Index of the first register added to NewRegs.
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const unsigned firstNew_;
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const unsigned FirstNew;
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/// scannedRemattable_ - true when remattable values have been identified.
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/// ScannedRemattable - true when remattable values have been identified.
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bool scannedRemattable_;
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bool ScannedRemattable;
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/// remattable_ - Values defined by remattable instructions as identified by
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/// Remattable - Values defined by remattable instructions as identified by
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/// tii.isTriviallyReMaterializable().
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/// tii.isTriviallyReMaterializable().
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SmallPtrSet<const VNInfo*,4> remattable_;
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SmallPtrSet<const VNInfo*,4> Remattable;
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/// rematted_ - Values that were actually rematted, and so need to have their
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/// Rematted - Values that were actually rematted, and so need to have their
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/// live range trimmed or entirely removed.
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/// live range trimmed or entirely removed.
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SmallPtrSet<const VNInfo*,4> rematted_;
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SmallPtrSet<const VNInfo*,4> Rematted;
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/// scanRemattable - Identify the parent_ values that may rematerialize.
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/// scanRemattable - Identify the Parent values that may rematerialize.
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void scanRemattable(AliasAnalysis *aa);
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void scanRemattable(AliasAnalysis *aa);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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@ -105,26 +105,26 @@ public:
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LiveIntervals &lis,
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LiveIntervals &lis,
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VirtRegMap *vrm,
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VirtRegMap *vrm,
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Delegate *delegate = 0)
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Delegate *delegate = 0)
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: parent_(parent), newRegs_(newRegs),
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: Parent(parent), NewRegs(newRegs),
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MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
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MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
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TII(*MF.getTarget().getInstrInfo()),
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TII(*MF.getTarget().getInstrInfo()),
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delegate_(delegate),
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TheDelegate(delegate),
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firstNew_(newRegs.size()),
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FirstNew(newRegs.size()),
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scannedRemattable_(false) {}
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ScannedRemattable(false) {}
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LiveInterval &getParent() const { return parent_; }
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LiveInterval &getParent() const { return Parent; }
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unsigned getReg() const { return parent_.reg; }
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unsigned getReg() const { return Parent.reg; }
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/// Iterator for accessing the new registers added by this edit.
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/// Iterator for accessing the new registers added by this edit.
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typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
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typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
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iterator begin() const { return newRegs_.begin()+firstNew_; }
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iterator begin() const { return NewRegs.begin()+FirstNew; }
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iterator end() const { return newRegs_.end(); }
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iterator end() const { return NewRegs.end(); }
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unsigned size() const { return newRegs_.size()-firstNew_; }
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unsigned size() const { return NewRegs.size()-FirstNew; }
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bool empty() const { return size() == 0; }
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bool empty() const { return size() == 0; }
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LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
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LiveInterval *get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
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ArrayRef<LiveInterval*> regs() const {
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ArrayRef<LiveInterval*> regs() const {
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return makeArrayRef(newRegs_).slice(firstNew_);
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return makeArrayRef(NewRegs).slice(FirstNew);
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}
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}
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/// createFrom - Create a new virtual register based on OldReg.
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/// createFrom - Create a new virtual register based on OldReg.
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@ -174,12 +174,12 @@ public:
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// it manually.
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/// it manually.
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void markRematerialized(const VNInfo *ParentVNI) {
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void markRematerialized(const VNInfo *ParentVNI) {
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rematted_.insert(ParentVNI);
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Rematted.insert(ParentVNI);
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}
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}
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/// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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/// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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bool didRematerialize(const VNInfo *ParentVNI) const {
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bool didRematerialize(const VNInfo *ParentVNI) const {
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return rematted_.count(ParentVNI);
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return Rematted.count(ParentVNI);
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}
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}
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/// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
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/// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
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@ -38,7 +38,7 @@ LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg) {
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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}
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}
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LiveInterval &LI = LIS.getOrCreateInterval(VReg);
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LiveInterval &LI = LIS.getOrCreateInterval(VReg);
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newRegs_.push_back(&LI);
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NewRegs.push_back(&LI);
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return LI;
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return LI;
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}
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}
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@ -46,16 +46,16 @@ bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
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const MachineInstr *DefMI,
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const MachineInstr *DefMI,
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AliasAnalysis *aa) {
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AliasAnalysis *aa) {
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assert(DefMI && "Missing instruction");
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assert(DefMI && "Missing instruction");
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scannedRemattable_ = true;
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ScannedRemattable = true;
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if (!TII.isTriviallyReMaterializable(DefMI, aa))
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if (!TII.isTriviallyReMaterializable(DefMI, aa))
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return false;
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return false;
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remattable_.insert(VNI);
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Remattable.insert(VNI);
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return true;
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return true;
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}
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}
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void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
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void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
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for (LiveInterval::vni_iterator I = parent_.vni_begin(),
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for (LiveInterval::vni_iterator I = Parent.vni_begin(),
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E = parent_.vni_end(); I != E; ++I) {
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E = Parent.vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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VNInfo *VNI = *I;
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if (VNI->isUnused())
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if (VNI->isUnused())
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continue;
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continue;
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@ -64,13 +64,13 @@ void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
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continue;
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continue;
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checkRematerializable(VNI, DefMI, aa);
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checkRematerializable(VNI, DefMI, aa);
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}
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}
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scannedRemattable_ = true;
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ScannedRemattable = true;
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}
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}
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bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
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bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
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if (!scannedRemattable_)
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if (!ScannedRemattable)
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scanRemattable(aa);
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scanRemattable(aa);
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return !remattable_.empty();
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return !Remattable.empty();
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}
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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@ -101,10 +101,10 @@ bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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bool LiveRangeEdit::canRematerializeAt(Remat &RM,
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bool LiveRangeEdit::canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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SlotIndex UseIdx,
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bool cheapAsAMove) {
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bool cheapAsAMove) {
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assert(scannedRemattable_ && "Call anyRematerializable first");
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assert(ScannedRemattable && "Call anyRematerializable first");
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// Use scanRemattable info.
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// Use scanRemattable info.
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if (!remattable_.count(RM.ParentVNI))
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if (!Remattable.count(RM.ParentVNI))
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return false;
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return false;
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// No defining instruction provided.
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// No defining instruction provided.
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@ -136,13 +136,13 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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bool Late) {
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bool Late) {
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assert(RM.OrigMI && "Invalid remat");
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assert(RM.OrigMI && "Invalid remat");
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TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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rematted_.insert(RM.ParentVNI);
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Rematted.insert(RM.ParentVNI);
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return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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.getRegSlot();
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.getRegSlot();
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}
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}
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void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
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void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
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if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
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if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
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LIS.removeInterval(Reg);
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LIS.removeInterval(Reg);
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}
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}
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@ -242,8 +242,8 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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// Remove defined value.
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// Remove defined value.
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if (MOI->isDef()) {
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if (MOI->isDef()) {
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if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
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if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
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if (delegate_)
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if (TheDelegate)
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delegate_->LRE_WillShrinkVirtReg(LI.reg);
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TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
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LI.removeValNo(VNI);
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LI.removeValNo(VNI);
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if (LI.empty()) {
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if (LI.empty()) {
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ToShrink.remove(&LI);
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ToShrink.remove(&LI);
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@ -253,8 +253,8 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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}
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}
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}
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}
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if (delegate_)
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if (TheDelegate)
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delegate_->LRE_WillEraseInstruction(MI);
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TheDelegate->LRE_WillEraseInstruction(MI);
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LIS.RemoveMachineInstrFromMaps(MI);
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LIS.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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MI->eraseFromParent();
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++NumDCEDeleted;
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++NumDCEDeleted;
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@ -268,8 +268,8 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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ToShrink.pop_back();
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ToShrink.pop_back();
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if (foldAsLoad(LI, Dead))
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if (foldAsLoad(LI, Dead))
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continue;
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continue;
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if (delegate_)
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if (TheDelegate)
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delegate_->LRE_WillShrinkVirtReg(LI->reg);
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TheDelegate->LRE_WillShrinkVirtReg(LI->reg);
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if (!LIS.shrinkToUses(LI, &Dead))
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if (!LIS.shrinkToUses(LI, &Dead))
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continue;
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continue;
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@ -304,8 +304,8 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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// interval must contain all the split products, and LI doesn't.
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// interval must contain all the split products, and LI doesn't.
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if (IsOriginal)
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if (IsOriginal)
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VRM->setIsSplitFromReg(Dups.back()->reg, 0);
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VRM->setIsSplitFromReg(Dups.back()->reg, 0);
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if (delegate_)
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if (TheDelegate)
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delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
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TheDelegate->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
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}
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}
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ConEQ.Distribute(&Dups[0], MRI);
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ConEQ.Distribute(&Dups[0], MRI);
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}
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}
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