mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
553d8007ad
commit
c6fd6cd65c
@ -369,105 +369,6 @@ static mu magicu64(uint64_t d)
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return magu;
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}
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/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. Op and Mask are known to
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/// be the same type.
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static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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const TargetLowering &TLI) {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// If either of the operands has zero bits, the result will too.
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if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
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MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
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return true;
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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return false;
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::ADD:
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// (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
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if ((Mask&(Mask+1)) == 0) { // All low bits
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if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
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return true;
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}
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break;
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case ISD::SUB:
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if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
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// We know that the top bits of C-X are clear if X contains less bits
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// than C (i.e. no wrap-around can happen). For example, 20-X is
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// positive if we can prove that X is >= 0 and < 16.
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unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
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if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
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unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
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uint64_t MaskV = (1ULL << (63-NLZ))-1;
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if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
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// High bits are clear this value is known to be >= C.
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unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
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if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
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return true;
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}
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}
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}
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break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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default:
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
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return TLI.isMaskedValueZeroForTargetNode(Op, Mask, MaskedValueIsZero);
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break;
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}
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return false;
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}
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// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
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// that selects between the values 1 and 0, making it equivalent to a setcc.
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// Also, set the incoming LHS, RHS, and CC references to the appropriate
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@ -812,8 +713,8 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
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// If we know the sign bits of both operands are zero, strength reduce to a
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// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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if (MaskedValueIsZero(N1, SignBit, TLI) &&
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MaskedValueIsZero(N0, SignBit, TLI))
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if (TLI.MaskedValueIsZero(N1, SignBit) &&
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TLI.MaskedValueIsZero(N0, SignBit))
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return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
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// fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1))
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if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
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@ -888,8 +789,8 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) {
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// If we know the sign bits of both operands are zero, strength reduce to a
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// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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if (MaskedValueIsZero(N1, SignBit, TLI) &&
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MaskedValueIsZero(N0, SignBit, TLI))
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if (TLI.MaskedValueIsZero(N1, SignBit) &&
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TLI.MaskedValueIsZero(N0, SignBit))
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return DAG.getNode(ISD::UREM, VT, N0, N1);
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return SDOperand();
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}
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@ -959,11 +860,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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if (N1C && N1C->isAllOnesValue())
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return N0;
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// if (and x, c) is known to be zero, return 0
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if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
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if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
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return DAG.getConstant(0, VT);
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// fold (and x, c) -> x iff (x & ~c) == 0
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if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
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TLI))
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if (N1C &&
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TLI.MaskedValueIsZero(N0, ~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
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return N0;
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// fold (and (and x, c1), c2) -> (and x, c1^c2)
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if (N1C && N0.getOpcode() == ISD::AND) {
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@ -1050,8 +951,8 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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// If the RHS of the AND has zeros where the sign bits of the SRA will
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// land, turn the SRA into an SRL.
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if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
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(~0ULL>>(64-OpSizeInBits)), TLI)) {
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if (TLI.MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
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(~0ULL>>(64-OpSizeInBits)))) {
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WorkList.push_back(N);
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CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
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N0.getOperand(1)));
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@ -1064,7 +965,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
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if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
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(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
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SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
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N0.getOperand(1), N0.getOperand(2),
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@ -1079,7 +980,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
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if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
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(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
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SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
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N0.getOperand(1), N0.getOperand(2),
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@ -1114,8 +1015,8 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
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if (N1C && N1C->isAllOnesValue())
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return N1;
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// fold (or x, c) -> c iff (x & ~c) == 0
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if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
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TLI))
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if (N1C &&
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TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
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return N1;
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// fold (or (or x, c1), c2) -> (or x, c1|c2)
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if (N1C && N0.getOpcode() == ISD::OR) {
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@ -1319,7 +1220,7 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
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if (N1C && N1C->isNullValue())
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return N0;
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// if (shl x, c) is known to be zero, return 0
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if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
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if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
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return DAG.getConstant(0, VT);
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// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
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if (N1C && N0.getOpcode() == ISD::SHL &&
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@ -1377,7 +1278,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
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if (N1C && N1C->isNullValue())
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return N0;
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// If the sign bit is known to be zero, switch this to a SRL.
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if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
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if (TLI.MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1))))
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return DAG.getNode(ISD::SRL, VT, N0, N1);
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return SDOperand();
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}
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@ -1403,7 +1304,7 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
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if (N1C && N1C->isNullValue())
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return N0;
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// if (srl x, c) is known to be zero, return 0
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if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
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if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
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return DAG.getConstant(0, VT);
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// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
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if (N1C && N0.getOpcode() == ISD::SRL &&
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@ -1544,7 +1445,7 @@ SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
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MVT::ValueType VT = LHSLo.getValueType();
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// fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
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if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
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SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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@ -1552,7 +1453,7 @@ SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
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return SDOperand();
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}
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// fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
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if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
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SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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@ -1568,7 +1469,7 @@ SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
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MVT::ValueType VT = LHSLo.getValueType();
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// fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
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if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
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SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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@ -1704,7 +1605,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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TargetLowering::ZeroOrNegativeOneSetCCResult)
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return N0;
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// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
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if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
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if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
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return DAG.getNode(ISD::AND, N0.getValueType(), N0,
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DAG.getConstant(~0ULL >> (64-EVTBits), VT));
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// fold (sext_in_reg (srl x)) -> sra x
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@ -2683,7 +2584,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
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// If we know that all of the inverted bits are zero, don't bother
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// performing the inversion.
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if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
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if (TLI.MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue()))
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return DAG.getSetCC(VT, N0.getOperand(0),
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DAG.getConstant(XORC->getValue()^RHSC->getValue(),
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N0.getValueType()), Cond);
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@ -16,6 +16,7 @@
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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TargetLowering::TargetLowering(TargetMachine &tm)
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@ -130,9 +131,113 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return NULL;
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}
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/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. Op and Mask are known to
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/// be the same type.
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bool TargetLowering::MaskedValueIsZero(const SDOperand &Op,
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uint64_t Mask) const {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)));
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// If either of the operands has zero bits, the result will too.
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if (MaskedValueIsZero(Op.getOperand(1), Mask) ||
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MaskedValueIsZero(Op.getOperand(0), Mask))
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return true;
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask);
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return false;
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask) &&
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MaskedValueIsZero(Op.getOperand(1), Mask);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask) &&
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MaskedValueIsZero(Op.getOperand(2), Mask);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask) &&
|
||||
MaskedValueIsZero(Op.getOperand(3), Mask);
|
||||
case ISD::SRL:
|
||||
// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
|
||||
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
||||
uint64_t NewVal = Mask << ShAmt->getValue();
|
||||
SrcBits = MVT::getSizeInBits(Op.getValueType());
|
||||
if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
|
||||
return MaskedValueIsZero(Op.getOperand(0), NewVal);
|
||||
}
|
||||
return false;
|
||||
case ISD::SHL:
|
||||
// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
|
||||
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
||||
uint64_t NewVal = Mask >> ShAmt->getValue();
|
||||
return MaskedValueIsZero(Op.getOperand(0), NewVal);
|
||||
}
|
||||
return false;
|
||||
case ISD::ADD:
|
||||
// (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
|
||||
if ((Mask&(Mask+1)) == 0) { // All low bits
|
||||
if (MaskedValueIsZero(Op.getOperand(0), Mask) &&
|
||||
MaskedValueIsZero(Op.getOperand(1), Mask))
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case ISD::SUB:
|
||||
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
|
||||
// We know that the top bits of C-X are clear if X contains less bits
|
||||
// than C (i.e. no wrap-around can happen). For example, 20-X is
|
||||
// positive if we can prove that X is >= 0 and < 16.
|
||||
unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
|
||||
if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
|
||||
unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
|
||||
uint64_t MaskV = (1ULL << (63-NLZ))-1;
|
||||
if (MaskedValueIsZero(Op.getOperand(1), ~MaskV)) {
|
||||
// High bits are clear this value is known to be >= C.
|
||||
unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
|
||||
if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ISD::CTTZ:
|
||||
case ISD::CTLZ:
|
||||
case ISD::CTPOP:
|
||||
// Bit counting instructions can not set the high bits of the result
|
||||
// register. The max number of bits sets depends on the input.
|
||||
return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
|
||||
default:
|
||||
// Allow the target to implement this method for its nodes.
|
||||
if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
|
||||
return isMaskedValueZeroForTargetNode(Op, Mask);
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
|
||||
uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const {
|
||||
uint64_t Mask) const {
|
||||
assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
|
||||
"Should use MaskedValueIsZero if you don't know whether Op"
|
||||
" is a target node!");
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
@ -62,8 +62,7 @@ namespace {
|
||||
/// be zero. Op is expected to be a target specific node. Used by DAG
|
||||
/// combiner.
|
||||
virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
|
||||
uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const;
|
||||
uint64_t Mask) const;
|
||||
|
||||
virtual std::vector<SDOperand>
|
||||
LowerArguments(Function &F, SelectionDAG &DAG);
|
||||
@ -203,16 +202,15 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
/// be zero. Op is expected to be a target specific node. Used by DAG
|
||||
/// combiner.
|
||||
bool SparcV8TargetLowering::
|
||||
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const {
|
||||
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
|
||||
switch (Op.getOpcode()) {
|
||||
default: return false;
|
||||
case V8ISD::SELECT_ICC:
|
||||
case V8ISD::SELECT_FCC:
|
||||
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
|
||||
// These operations are masked zero if both the left and the right are zero.
|
||||
return MVIZ(Op.getOperand(0), Mask, *this) &&
|
||||
MVIZ(Op.getOperand(1), Mask, *this);
|
||||
return MaskedValueIsZero(Op.getOperand(0), Mask) &&
|
||||
MaskedValueIsZero(Op.getOperand(1), Mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -62,8 +62,7 @@ namespace {
|
||||
/// be zero. Op is expected to be a target specific node. Used by DAG
|
||||
/// combiner.
|
||||
virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
|
||||
uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const;
|
||||
uint64_t Mask) const;
|
||||
|
||||
virtual std::vector<SDOperand>
|
||||
LowerArguments(Function &F, SelectionDAG &DAG);
|
||||
@ -203,16 +202,15 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
/// be zero. Op is expected to be a target specific node. Used by DAG
|
||||
/// combiner.
|
||||
bool SparcV8TargetLowering::
|
||||
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const {
|
||||
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
|
||||
switch (Op.getOpcode()) {
|
||||
default: return false;
|
||||
case V8ISD::SELECT_ICC:
|
||||
case V8ISD::SELECT_FCC:
|
||||
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
|
||||
// These operations are masked zero if both the left and the right are zero.
|
||||
return MVIZ(Op.getOperand(0), Mask, *this) &&
|
||||
MVIZ(Op.getOperand(1), Mask, *this);
|
||||
return MaskedValueIsZero(Op.getOperand(0), Mask) &&
|
||||
MaskedValueIsZero(Op.getOperand(1), Mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1932,8 +1932,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
|
||||
bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
|
||||
uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const {
|
||||
uint64_t Mask) const {
|
||||
|
||||
unsigned Opc = Op.getOpcode();
|
||||
|
||||
|
||||
@ -208,8 +208,7 @@ namespace llvm {
|
||||
/// be zero. Op is expected to be a target specific node. Used by DAG
|
||||
/// combiner.
|
||||
virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
|
||||
uint64_t Mask,
|
||||
MVIZFnPtr MVIZ) const;
|
||||
uint64_t Mask) const;
|
||||
|
||||
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user