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AVX-512: fixed UINT_TO_FP operation for 512-bit types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236955 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-05-10 14:23:52 +00:00
parent a0adcdb9ce
commit c7c44fa75e
2 changed files with 24 additions and 0 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1301,6 +1301,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
@ -11793,6 +11795,11 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
case MVT::v4i32:
case MVT::v8i32:
return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
case MVT::v16i8:
case MVT::v16i16:
if (Subtarget->hasAVX512())
return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
}
llvm_unreachable(nullptr);
}

17
test/CodeGen/X86/avx512-cvt.ll
View File

@ -308,3 +308,20 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) {
%1 = sitofp <8 x i1> %cmpres to <8 x double>
ret <8 x double> %1
}
; CHECK-LABEL: @uitofp_16i8
; CHECK: vpmovzxbd
; CHECK: vcvtudq2ps
define <16 x float> @uitofp_16i8(<16 x i8>%a) {
%b = uitofp <16 x i8> %a to <16 x float>
ret <16 x float>%b
}
; CHECK-LABEL: @uitofp_16i16
; CHECK: vpmovzxwd
; CHECK: vcvtudq2ps
define <16 x float> @uitofp_16i16(<16 x i16>%a) {
%b = uitofp <16 x i16> %a to <16 x float>
ret <16 x float>%b
}