mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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de4845c163
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c7f3ace20c
@ -312,7 +312,7 @@ ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc argument
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DebugLoc dl = DebugLoc::getUnknownLoc();
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DebugLoc dl;
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ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
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int BOpc = !AFI->isThumbFunction()
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@ -653,7 +653,7 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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// tGPR is used sometimes in ARM instructions that need to avoid using
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@ -715,7 +715,7 @@ void ARMBaseInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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@ -769,7 +769,7 @@ void ARMBaseInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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@ -1277,8 +1277,7 @@ emitPrologue(MachineFunction &MF) const {
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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unsigned NumBytes = MFI->getStackSize();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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DebugLoc dl = (MBBI != MBB.end() ?
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MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Determine the sizes of each callee-save spill areas and record which frame
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// belongs to which callee-save spill areas.
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@ -399,7 +399,7 @@ void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
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// aligned.
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assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
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MachineInstr *CPEMI =
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BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
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BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
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.addImm(i).addConstantPoolIndex(i).addImm(Size);
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CPEMIs.push_back(CPEMI);
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@ -721,7 +721,7 @@ MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
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// There doesn't seem to be meaningful DebugInfo available; this doesn't
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// correspond to anything in the source.
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unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
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BuildMI(OrigBB, DebugLoc::getUnknownLoc(), TII->get(Opc)).addMBB(NewBB);
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BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
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NumSplit++;
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// Update the CFG. All succs of OrigBB are now succs of NewBB.
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@ -1103,8 +1103,7 @@ void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
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// targets will be exchanged, and the altered branch may be out of
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// range, so the machinery has to know about it.
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int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
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BuildMI(UserMBB, DebugLoc::getUnknownLoc(),
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TII->get(UncondBr)).addMBB(NewMBB);
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BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
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unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
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ImmBranches.push_back(ImmBranch(&UserMBB->back(),
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MaxDisp, false, UncondBr));
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@ -1244,8 +1243,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
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// Now that we have an island to add the CPE to, clone the original CPE and
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// add it to the island.
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U.HighWaterMark = NewIsland;
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U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(),
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TII->get(ARM::CONSTPOOL_ENTRY))
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U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
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.addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
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CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
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NumCPEs++;
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@ -1446,12 +1444,11 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
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// Insert a new conditional branch and a new unconditional branch.
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// Also update the ImmBranch as well as adding a new entry for the new branch.
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BuildMI(MBB, DebugLoc::getUnknownLoc(),
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TII->get(MI->getOpcode()))
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BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
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.addMBB(NextBB).addImm(CC).addReg(CCReg);
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Br.MI = &MBB->back();
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BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
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BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
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BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
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BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
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unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
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ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
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@ -1809,7 +1806,7 @@ AdjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB)
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// There doesn't seem to be meaningful DebugInfo available; this doesn't
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// correspond directly to anything in the source.
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assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
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BuildMI(NewBB, DebugLoc::getUnknownLoc(), TII->get(ARM::t2B)).addMBB(BB);
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BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
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// Update internal data structures to account for the newly inserted MBB.
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MF.RenumberBlocks(NewBB);
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@ -37,7 +37,7 @@ bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == ARM::GPRRegisterClass) {
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@ -98,7 +98,7 @@ void Thumb1InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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assert((RC == ARM::tGPRRegisterClass ||
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@ -125,7 +125,7 @@ void Thumb1InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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assert((RC == ARM::tGPRRegisterClass ||
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@ -154,7 +154,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (CSI.empty())
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return false;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
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@ -398,7 +398,7 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
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// off the frame pointer (if, for example, there are alloca() calls in
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// the function, the offset will be negative. Use R12 instead since that's
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// a call clobbered register that we know won't be used in Thumb1 mode.
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
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addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
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@ -685,8 +685,7 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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unsigned NumBytes = MFI->getStackSize();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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DebugLoc dl = (MBBI != MBB.end() ?
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MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
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NumBytes = (NumBytes + 3) & ~3;
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@ -41,7 +41,7 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == ARM::GPRRegisterClass &&
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@ -66,7 +66,7 @@ void Thumb2InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
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@ -90,7 +90,7 @@ void Thumb2InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
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@ -471,8 +471,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
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SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
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DAG.getNode(AlphaISD::GlobalRetAddr,
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DebugLoc::getUnknownLoc(),
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MVT::i64),
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DebugLoc(), MVT::i64),
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SDValue());
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switch (Outs.size()) {
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default:
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@ -740,8 +739,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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SA2, NULL, 0, MVT::i32, false, false, 0);
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}
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case ISD::RETURNADDR:
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return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
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MVT::i64);
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return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);
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//FIXME: implement
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case ISD::FRAMEADDR: break;
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}
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@ -112,7 +112,7 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc argument
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DebugLoc dl = DebugLoc::getUnknownLoc();
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DebugLoc dl;
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Alpha branch conditions have two components!");
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@ -153,7 +153,7 @@ bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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return false;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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if (DestRC == Alpha::GPRCRegisterClass) {
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@ -185,7 +185,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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// << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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if (RC == Alpha::F4RCRegisterClass)
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@ -211,7 +211,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC) const {
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//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
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// << FrameIdx << "\n";
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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if (RC == Alpha::F4RCRegisterClass)
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@ -398,7 +398,7 @@ unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
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.addReg(Alpha::R31)
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@ -49,7 +49,7 @@ namespace {
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const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
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bool Changed = false;
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MachineInstr* prev[3] = {0,0,0};
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DebugLoc dl = DebugLoc::getUnknownLoc();
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DebugLoc dl;
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unsigned count = 0;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI) {
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@ -207,8 +207,7 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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DebugLoc dl = (MBBI != MBB.end() ?
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MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
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DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
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bool FP = hasFP(MF);
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//handle GOP offset
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@ -106,7 +106,7 @@ InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc operand
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DebugLoc dl = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -116,7 +116,7 @@ InsertBranch(MachineBasicBlock &MBB,
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, dl, get(BF::JUMPa)).addMBB(TBB);
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BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB);
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return 1;
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}
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@ -139,27 +139,27 @@ bool BlackfinInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc dl = DebugLoc::getUnknownLoc();
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DebugLoc DL;
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if (inClass(BF::ALLRegClass, DestReg, DestRC) &&
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inClass(BF::ALLRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::MOVE), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::D16RegClass, DestReg, DestRC) &&
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inClass(BF::D16RegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
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BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg).addReg(SrcReg).addImm(0);
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return true;
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}
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if (inClass(BF::AnyCCRegClass, SrcReg, SrcRC) &&
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inClass(BF::DRegClass, DestReg, DestRC)) {
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if (inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, dl, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
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BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
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} else {
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BuildMI(MBB, I, dl, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg).addReg(SrcReg);
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}
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return true;
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}
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@ -167,21 +167,21 @@ bool BlackfinInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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if (inClass(BF::AnyCCRegClass, DestReg, DestRC) &&
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inClass(BF::DRegClass, SrcReg, SrcRC)) {
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if (inClass(BF::NotCCRegClass, DestReg, DestRC))
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BuildMI(MBB, I, dl, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg).addReg(SrcReg);
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else
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BuildMI(MBB, I, dl, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::NotCCRegClass, DestReg, DestRC) &&
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inClass(BF::JustCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg).addReg(SrcReg);
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return true;
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}
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if (inClass(BF::JustCCRegClass, DestReg, DestRC) &&
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inClass(BF::NotCCRegClass, SrcReg, SrcRC)) {
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BuildMI(MBB, I, dl, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg).addReg(SrcReg);
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return true;
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}
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@ -197,8 +197,7 @@ BlackfinInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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bool isKill,
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int FI,
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const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = I != MBB.end() ?
|
||||
I->getDebugLoc() : DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
|
||||
|
||||
if (inClass(BF::DPRegClass, SrcReg, RC)) {
|
||||
BuildMI(MBB, I, DL, get(BF::STORE32fi))
|
||||
@ -244,8 +243,7 @@ BlackfinInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
unsigned DestReg,
|
||||
int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = I != MBB.end() ?
|
||||
I->getDebugLoc() : DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
|
||||
if (inClass(BF::DPRegClass, DestReg, RC)) {
|
||||
BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
|
||||
.addFrameIndex(FI)
|
||||
|
@ -384,9 +384,7 @@ void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
DebugLoc dl = (MBBI != MBB.end()
|
||||
? MBBI->getDebugLoc()
|
||||
: DebugLoc::getUnknownLoc());
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
int FrameSize = MFI->getStackSize();
|
||||
if (FrameSize%4) {
|
||||
|
@ -262,7 +262,7 @@ bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
// we instruction select bitconvert i64 -> f64 as a noop for example, so our
|
||||
// types have no specific meaning.
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
if (DestRC == SPU::R8CRegisterClass) {
|
||||
@ -317,7 +317,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
llvm_unreachable("Unknown regclass!");
|
||||
}
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
addFrameReference(BuildMI(MBB, MI, DL, get(opc))
|
||||
.addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
|
||||
@ -351,7 +351,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
|
||||
}
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
|
||||
}
|
||||
@ -553,7 +553,7 @@ SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
|
@ -452,8 +452,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
||||
DebugLoc dl = (MBBI != MBB.end() ?
|
||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Prepare for debug frame info.
|
||||
bool hasDebugInfo = MMI && MMI->hasDebugInfo();
|
||||
|
@ -106,7 +106,7 @@ isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
|
||||
/// instruction.
|
||||
void MBlazeInstrInfo::
|
||||
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
BuildMI(MBB, MI, DL, get(MBlaze::NOP));
|
||||
}
|
||||
@ -116,8 +116,8 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
llvm::BuildMI(MBB, I, dl, get(MBlaze::ADD), DestReg)
|
||||
DebugLoc DL;
|
||||
llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
|
||||
.addReg(SrcReg).addReg(MBlaze::R0);
|
||||
return true;
|
||||
}
|
||||
@ -126,8 +126,8 @@ void MBlazeInstrInfo::
|
||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
BuildMI(MBB, I, dl, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
||||
DebugLoc DL;
|
||||
BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
||||
.addImm(0).addFrameIndex(FI);
|
||||
}
|
||||
|
||||
@ -135,8 +135,8 @@ void MBlazeInstrInfo::
|
||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
BuildMI(MBB, I, dl, get(MBlaze::LWI), DestReg)
|
||||
DebugLoc DL;
|
||||
BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
|
||||
.addImm(0).addFrameIndex(FI);
|
||||
}
|
||||
|
||||
@ -185,11 +185,9 @@ unsigned MBlazeInstrInfo::
|
||||
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
|
||||
// Can only insert uncond branches so far.
|
||||
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
|
||||
BuildMI(&MBB, dl, get(MBlaze::BRI)).addMBB(TBB);
|
||||
BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
@ -302,8 +302,7 @@ emitPrologue(MachineFunction &MF) const {
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc dl = (MBBI != MBB.end() ?
|
||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Get the right frame order for MBlaze.
|
||||
adjustMBlazeStackFrame(MF);
|
||||
@ -319,13 +318,13 @@ emitPrologue(MachineFunction &MF) const {
|
||||
int RAOffset = MBlazeFI->getRAStackOffset();
|
||||
|
||||
// Adjust stack : addi R1, R1, -imm
|
||||
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
|
||||
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
|
||||
.addReg(MBlaze::R1).addImm(-StackSize);
|
||||
|
||||
// Save the return address only if the function isnt a leaf one.
|
||||
// swi R15, R1, stack_loc
|
||||
if (MFI->hasCalls()) {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::SWI))
|
||||
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
|
||||
.addReg(MBlaze::R15).addImm(RAOffset).addReg(MBlaze::R1);
|
||||
}
|
||||
|
||||
@ -333,11 +332,11 @@ emitPrologue(MachineFunction &MF) const {
|
||||
// to point to the stack pointer
|
||||
if (hasFP(MF)) {
|
||||
// swi R19, R1, stack_loc
|
||||
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::SWI))
|
||||
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
|
||||
.addReg(MBlaze::R19).addImm(FPOffset).addReg(MBlaze::R1);
|
||||
|
||||
// add R19, R1, R0
|
||||
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R19)
|
||||
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
|
||||
.addReg(MBlaze::R1).addReg(MBlaze::R0);
|
||||
}
|
||||
}
|
||||
|
@ -33,7 +33,7 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
||||
@ -60,7 +60,7 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
||||
@ -86,7 +86,7 @@ bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (DestRC == SrcRC) {
|
||||
@ -134,7 +134,7 @@ MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
if (CSI.empty())
|
||||
return false;
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
@ -158,7 +158,7 @@ MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
if (CSI.empty())
|
||||
return false;
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
for (unsigned i = 0, e = CSI.size(); i != e; ++i)
|
||||
@ -323,7 +323,7 @@ MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc operand
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
@ -333,18 +333,18 @@ MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
assert(!FBB && "Unconditional branch with multiple successors!");
|
||||
BuildMI(&MBB, dl, get(MSP430::JMP)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Conditional branch.
|
||||
unsigned Count = 0;
|
||||
BuildMI(&MBB, dl, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
|
||||
BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
|
||||
++Count;
|
||||
|
||||
if (FBB) {
|
||||
// Two-way Conditional branch. Insert the second branch.
|
||||
BuildMI(&MBB, dl, get(MSP430::JMP)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
||||
++Count;
|
||||
}
|
||||
return Count;
|
||||
|
@ -283,8 +283,7 @@ void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
|
||||
DebugLoc::getUnknownLoc());
|
||||
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Get the number of bytes to allocate from the FrameInfo.
|
||||
uint64_t StackSize = MFI->getStackSize();
|
||||
|
@ -123,7 +123,7 @@ isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
void MipsInstrInfo::
|
||||
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
|
||||
{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
BuildMI(MBB, MI, DL, get(Mips::NOP));
|
||||
}
|
||||
@ -133,7 +133,7 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
@ -191,7 +191,7 @@ void MipsInstrInfo::
|
||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
@ -225,7 +225,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, int FI,
|
||||
const TargetRegisterClass *RC) const
|
||||
{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (RC == Mips::CPURegsRegisterClass)
|
||||
@ -523,7 +523,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
|
||||
|
@ -397,8 +397,7 @@ emitPrologue(MachineFunction &MF) const
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc dl = (MBBI != MBB.end() ?
|
||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
|
||||
|
||||
// Get the right frame order for Mips.
|
||||
|
@ -72,7 +72,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
PIC16TargetLowering *PTLI = TM.getTargetLowering();
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
const Function *Func = MBB.getParent()->getFunction();
|
||||
@ -114,7 +114,7 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
PIC16TargetLowering *PTLI = TM.getTargetLowering();
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
const Function *Func = MBB.getParent()->getFunction();
|
||||
@ -154,7 +154,7 @@ bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (DestRC == PIC16::FSR16RegisterClass) {
|
||||
@ -202,7 +202,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (FBB == 0) { // One way branch.
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
|
||||
}
|
||||
return 1;
|
||||
|
@ -215,7 +215,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
|
||||
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
MachineBasicBlock &EntryBB = *Fn.begin();
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Emit the following code into the entry block:
|
||||
// InVRSAVE = MFVRSAVE
|
||||
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
|
||||
@ -253,7 +253,7 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
|
||||
// Insert the set of GlobalBaseReg into the first MBB of the function
|
||||
MachineBasicBlock &FirstMBB = MF->front();
|
||||
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
|
||||
if (PPCLowering.getPointerTy() == MVT::i32) {
|
||||
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
|
||||
|
@ -1122,7 +1122,7 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
|
||||
// With PIC, the first instruction is actually "GR+hi(&G)".
|
||||
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
|
||||
DAG.getNode(PPCISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), PtrVT), Hi);
|
||||
DebugLoc(), PtrVT), Hi);
|
||||
}
|
||||
|
||||
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
|
||||
@ -1155,7 +1155,7 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
|
||||
// With PIC, the first instruction is actually "GR+hi(&G)".
|
||||
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
|
||||
DAG.getNode(PPCISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), PtrVT), Hi);
|
||||
DebugLoc(), PtrVT), Hi);
|
||||
}
|
||||
|
||||
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
|
||||
@ -1192,7 +1192,7 @@ SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
|
||||
// With PIC, the first instruction is actually "GR+hi(&G)".
|
||||
Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
|
||||
DAG.getNode(PPCISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), PtrVT), Hi);
|
||||
DebugLoc(), PtrVT), Hi);
|
||||
}
|
||||
|
||||
return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
|
||||
@ -1233,7 +1233,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
|
||||
// With PIC, the first instruction is actually "GR+hi(&G)".
|
||||
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
|
||||
DAG.getNode(PPCISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), PtrVT), Hi);
|
||||
DebugLoc(), PtrVT), Hi);
|
||||
}
|
||||
|
||||
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
|
||||
|
@ -199,7 +199,7 @@ PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
|
||||
|
||||
void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
BuildMI(MBB, MI, DL, get(PPC::NOP));
|
||||
@ -317,7 +317,7 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc argument
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -350,7 +350,7 @@ bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
return false;
|
||||
}
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
if (DestRC == PPC::GPRCRegisterClass) {
|
||||
@ -380,7 +380,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
|
||||
int FrameIdx,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (RC == PPC::GPRCRegisterClass) {
|
||||
if (SrcReg != PPC::LR) {
|
||||
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
|
||||
@ -635,7 +635,7 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
const TargetRegisterClass *RC) const {
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
SmallVector<MachineInstr*, 4> NewMIs;
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
|
||||
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
||||
|
@ -1281,7 +1281,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
|
||||
!MF.getFunction()->doesNotThrow() ||
|
||||
UnwindTablesMandatory;
|
||||
@ -1521,7 +1521,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const {
|
||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||
unsigned RetOpcode = MBBI->getOpcode();
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
|
||||
assert( (RetOpcode == PPC::BLR ||
|
||||
RetOpcode == PPC::TCRETURNri ||
|
||||
|
@ -68,7 +68,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
|
||||
if (I->getDesc().hasDelaySlot()) {
|
||||
MachineBasicBlock::iterator J = I;
|
||||
++J;
|
||||
BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP));
|
||||
BuildMI(MBB, J, DebugLoc(), TII->get(SP::NOP));
|
||||
++FilledSlots;
|
||||
Changed = true;
|
||||
}
|
||||
|
@ -111,7 +111,7 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond)const{
|
||||
// FIXME this should probably take a DebugLoc argument
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Can only insert uncond branches so far.
|
||||
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
|
||||
BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
|
||||
@ -128,7 +128,7 @@ bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
return false;
|
||||
}
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (DestRC == SP::IntRegsRegisterClass)
|
||||
@ -149,7 +149,7 @@ void SparcInstrInfo::
|
||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned SrcReg, bool isKill, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
||||
@ -170,7 +170,7 @@ void SparcInstrInfo::
|
||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, int FI,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (RC == SP::IntRegsRegisterClass)
|
||||
@ -253,7 +253,7 @@ unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
|
||||
GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
|
||||
|
||||
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
|
||||
BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
|
||||
SparcFI->setGlobalBaseReg(GlobalBaseReg);
|
||||
|
@ -125,8 +125,7 @@ void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineBasicBlock &MBB = MF.front();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc dl = (MBBI != MBB.end() ?
|
||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Get the number of bytes to allocate from the FrameInfo
|
||||
int NumBytes = (int) MFI->getStackSize();
|
||||
|
@ -62,7 +62,7 @@ void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
unsigned Opc = 0;
|
||||
@ -91,7 +91,7 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
unsigned DestReg, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
unsigned Opc = 0;
|
||||
@ -120,7 +120,7 @@ bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
// Determine if DstRC and SrcRC have a common superclass.
|
||||
@ -273,7 +273,7 @@ SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
if (CSI.empty())
|
||||
return false;
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
@ -347,7 +347,7 @@ SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
if (CSI.empty())
|
||||
return false;
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
@ -521,7 +521,7 @@ SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME: this should probably have a DebugLoc operand
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
@ -530,19 +530,19 @@ SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
if (Cond.empty()) {
|
||||
// Unconditional branch?
|
||||
assert(!FBB && "Unconditional branch with multiple successors!");
|
||||
BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Conditional branch.
|
||||
unsigned Count = 0;
|
||||
SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
|
||||
BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
|
||||
BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
|
||||
++Count;
|
||||
|
||||
if (FBB) {
|
||||
// Two-way Conditional branch. Insert the second branch.
|
||||
BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
|
||||
BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB);
|
||||
++Count;
|
||||
}
|
||||
return Count;
|
||||
|
@ -194,8 +194,7 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
||||
Chunk = (1LL << 15) - 1;
|
||||
}
|
||||
|
||||
DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
|
||||
DebugLoc::getUnknownLoc());
|
||||
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
while (Offset) {
|
||||
uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
|
||||
@ -215,8 +214,7 @@ void SystemZRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
SystemZMachineFunctionInfo *SystemZMFI =
|
||||
MF.getInfo<SystemZMachineFunctionInfo>();
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
|
||||
DebugLoc::getUnknownLoc());
|
||||
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Get the number of bytes to allocate from the FrameInfo.
|
||||
// Note that area for callee-saved stuff is already allocated, thus we need to
|
||||
|
@ -129,7 +129,7 @@ bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
|
||||
}
|
||||
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
|
||||
if (ContainsFPCode) {
|
||||
BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(),
|
||||
BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(),
|
||||
MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
|
||||
++NumFPKill;
|
||||
Changed = true;
|
||||
|
@ -542,7 +542,7 @@ void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
|
||||
MachineFrameInfo *MFI) {
|
||||
const TargetInstrInfo *TII = TM.getInstrInfo();
|
||||
if (Subtarget->isTargetCygMing())
|
||||
BuildMI(BB, DebugLoc::getUnknownLoc(),
|
||||
BuildMI(BB, DebugLoc(),
|
||||
TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
|
||||
}
|
||||
|
||||
|
@ -1149,8 +1149,7 @@ SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
|
||||
if (!Subtarget->is64Bit())
|
||||
// This doesn't have DebugLoc associated with it, but is not really the
|
||||
// same as a Register.
|
||||
return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
|
||||
getPointerTy());
|
||||
return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
|
||||
return Table;
|
||||
}
|
||||
|
||||
@ -1931,8 +1930,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
if (!isTailCall) {
|
||||
Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
|
||||
DAG.getNode(X86ISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(),
|
||||
getPointerTy()),
|
||||
DebugLoc(), getPointerTy()),
|
||||
InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
} else {
|
||||
@ -5061,7 +5059,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
|
||||
if (OpFlag) {
|
||||
Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
|
||||
DAG.getNode(X86ISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), getPointerTy()),
|
||||
DebugLoc(), getPointerTy()),
|
||||
Result);
|
||||
}
|
||||
|
||||
@ -5094,7 +5092,7 @@ SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
|
||||
if (OpFlag) {
|
||||
Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
|
||||
DAG.getNode(X86ISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(), getPointerTy()),
|
||||
DebugLoc(), getPointerTy()),
|
||||
Result);
|
||||
}
|
||||
|
||||
@ -5130,8 +5128,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
|
||||
!Subtarget->is64Bit()) {
|
||||
Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
|
||||
DAG.getNode(X86ISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(),
|
||||
getPointerTy()),
|
||||
DebugLoc(), getPointerTy()),
|
||||
Result);
|
||||
}
|
||||
|
||||
@ -5253,8 +5250,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
||||
DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
|
||||
SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
|
||||
DAG.getNode(X86ISD::GlobalBaseReg,
|
||||
DebugLoc::getUnknownLoc(),
|
||||
PtrVT), InFlag);
|
||||
DebugLoc(), PtrVT), InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
|
||||
return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
|
||||
@ -5276,7 +5272,7 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
||||
DebugLoc dl = GA->getDebugLoc();
|
||||
// Get the Thread Pointer
|
||||
SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
|
||||
DebugLoc::getUnknownLoc(), PtrVT,
|
||||
DebugLoc(), PtrVT,
|
||||
DAG.getRegister(is64Bit? X86::FS : X86::GS,
|
||||
MVT::i32));
|
||||
|
||||
|
@ -1803,7 +1803,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
// FIXME this should probably have a DebugLoc operand
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
@ -2107,7 +2107,7 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
bool isAligned = (*MMOBegin)->getAlignment() >= 16;
|
||||
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
|
||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||
MIB.addOperand(Addr[i]);
|
||||
@ -2202,7 +2202,7 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
bool isAligned = (*MMOBegin)->getAlignment() >= 16;
|
||||
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
|
||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||
MIB.addOperand(Addr[i]);
|
||||
|
@ -301,7 +301,7 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond)const{
|
||||
// FIXME there should probably be a DebugLoc argument here
|
||||
DebugLoc dl = DebugLoc::getUnknownLoc();
|
||||
DebugLoc dl;
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
||||
@ -362,7 +362,7 @@ bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const {
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (DestRC == SrcRC) {
|
||||
@ -397,7 +397,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
int FrameIndex,
|
||||
const TargetRegisterClass *RC) const
|
||||
{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
BuildMI(MBB, I, DL, get(XCore::STWFI))
|
||||
.addReg(SrcReg, getKillRegState(isKill))
|
||||
@ -410,7 +410,7 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const
|
||||
{
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
|
||||
.addFrameIndex(FrameIndex)
|
||||
@ -431,7 +431,7 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
|
||||
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
|
||||
|
||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||
DebugLoc DL;
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
|
||||
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
|
||||
|
@ -414,8 +414,7 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
||||
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
|
||||
DebugLoc dl = (MBBI != MBB.end() ?
|
||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
bool FP = hasFP(MF);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user