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[mips] Remove predicates that were incorrectly or unnecessarily added.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-08-20 23:21:55 +00:00
parent 328a4fbfbb
commit c89cb45ecb
3 changed files with 6 additions and 6 deletions
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2
lib/Target/Mips/Mips64InstrInfo.td
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@@ -288,7 +288,7 @@ defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
// truncate // truncate
def : MipsPat<(i32 (trunc GPR64:$src)), def : MipsPat<(i32 (trunc GPR64:$src)),
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
Requires<[IsN64, HasStdEnc]>; Requires<[HasStdEnc]>;
// 32-to-64-bit extension // 32-to-64-bit extension
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;

2
lib/Target/Mips/MipsCallingConv.td
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@@ -27,7 +27,7 @@ def RetCC_MipsO32 : CallingConv<[
CCIfType<[f32], CCAssignToReg<[F0, F2]>>, CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
// f64 are returned in register D0, D1 // f64 are returned in register D0, D1
CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>> CCIfType<[f64], CCAssignToReg<[D0, D1]>>
]>; ]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

8
lib/Target/Mips/MipsInstrFPU.td
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@@ -358,12 +358,12 @@ let Predicates = [HasStdEnc] in {
def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>; def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>;
} }
let Predicates = [HasMips64, HasStdEnc], DecoderNamespace = "Mips64" in { let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>; def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>;
def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>; def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
} }
let Predicates = [NotMips64, HasStdEnc] in { let Predicates = [NotFP64bit, HasStdEnc] in {
let isPseudo = 1, isCodeGenOnly = 1 in { let isPseudo = 1, isCodeGenOnly = 1 in {
def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, load>; def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, load>;
def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, store>; def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, store>;
@@ -600,12 +600,12 @@ let AddedComplexity = 40 in {
def : StoreRegImmPat<SWC1, f32>; def : StoreRegImmPat<SWC1, f32>;
} }
let Predicates = [HasMips64, HasStdEnc] in { let Predicates = [IsFP64bit, HasStdEnc] in {
def : LoadRegImmPat<LDC164, f64, load>; def : LoadRegImmPat<LDC164, f64, load>;
def : StoreRegImmPat<SDC164, f64>; def : StoreRegImmPat<SDC164, f64>;
} }
let Predicates = [NotMips64, HasStdEnc] in { let Predicates = [NotFP64bit, HasStdEnc] in {
def : LoadRegImmPat<PseudoLDC1, f64, load>; def : LoadRegImmPat<PseudoLDC1, f64, load>;
def : StoreRegImmPat<PseudoSDC1, f64>; def : StoreRegImmPat<PseudoSDC1, f64>;
} }