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Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27133 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -539,6 +539,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
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DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
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// Find a register to spill.
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float minWeight = float(HUGE_VAL);
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float minWeight = float(HUGE_VAL);
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unsigned minReg = 0;
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unsigned minReg = 0;
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for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
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for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
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@ -549,6 +550,9 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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minReg = reg;
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minReg = reg;
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}
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}
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}
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}
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// If we didn't find a register that is spillable, try aliases?
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// FIXME: assert(minReg && "Didn't find any reg!");
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// FIXME: assert(minReg && "Didn't find any reg!");
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DEBUG(std::cerr << "\t\tregister with min weight: "
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DEBUG(std::cerr << "\t\tregister with min weight: "
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<< mri_->getName(minReg) << " (" << minWeight << ")\n");
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<< mri_->getName(minReg) << " (" << minWeight << ")\n");
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