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Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138723 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -618,14 +618,32 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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// Emit segment override opcode prefix as needed.
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switch (Desc->TSFlags & X86II::SegOvrMask) {
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case X86II::FS:
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MCE.emitByte(0x64);
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case 0: {
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// Determine where the memory operand starts, if present.
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int MemOperand = X86II::getMemoryOperandNo(Desc->TSFlags);
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// No segment override, check for explicit one on memory operand.
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if (MemOperand != -1) { // If the instruction has a memory operand.
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switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
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default: assert(0 && "Unknown segment register!");
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case 0: break;
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case X86::CS: MCE.emitByte(0x2E); break;
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case X86::SS: MCE.emitByte(0x36); break;
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case X86::DS: MCE.emitByte(0x3E); break;
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case X86::ES: MCE.emitByte(0x26); break;
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case X86::FS: MCE.emitByte(0x64); break;
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case X86::GS: MCE.emitByte(0x65); break;
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}
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}
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}
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break;
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case X86II::GS:
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MCE.emitByte(0x65);
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break;
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default: llvm_unreachable("Invalid segment!");
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case 0: break; // No segment override!
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case X86II::FS:
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MCE.emitByte(0x64);
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break;
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case X86II::GS:
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MCE.emitByte(0x65);
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break;
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default: llvm_unreachable("Invalid segment!");
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}
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// Emit the repeat opcode prefix as needed.
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