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implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1281,6 +1281,44 @@ ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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// ARM Optimization Hooks
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//===----------------------------------------------------------------------===//
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const {
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if (!isLegalAddressImmediate(AM.BaseOffs, Ty))
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return false;
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// Can never fold addr of global into load/store.
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if (AM.BaseGV)
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return false;
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switch (AM.Scale) {
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case 0: // no scale reg, must be "r+i" or "r", or "i".
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break;
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case 1:
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if (Subtarget->isThumb())
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return false;
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default:
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// FIXME: verify.
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switch (getValueType(Ty)) {
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default: return false;
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case MVT::i1:
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case MVT::i8:
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// TODO: i16? i64 should be i32, no?
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case MVT::i32:
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// r + r
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if (AM.Scale == 2)
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return true;
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// r + r << imm
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if (!isPowerOf2_32(AM.Scale & ~1))
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return false;
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}
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break;
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}
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return true;
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}
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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@ -80,6 +80,10 @@ namespace llvm {
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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@ -3199,6 +3199,39 @@ isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
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return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
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}
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// isLegalAddressingMode - Return true if the addressing mode represented
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// by AM is legal for this target, for a load/store of the specified type.
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bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const {
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// FIXME: PPC does not allow r+i addressing modes for vectors!
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// PPC allows a sign-extended 16-bit immediate field.
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if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
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return false;
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// No global is ever allowed as a base.
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if (AM.BaseGV)
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return false;
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// PPC only support r+r,
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switch (AM.Scale) {
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case 0: // "r+i" or just "i", depending on HasBaseReg.
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break;
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case 1:
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if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
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return false;
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// Otherwise we have r+r or r+i.
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break;
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case 2:
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if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
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return false;
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// Allow 2*r as r+r.
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break;
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}
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return true;
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}
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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@ -3208,7 +3241,7 @@ bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
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}
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bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
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return TargetLowering::isLegalAddressImmediate(GV);
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return false;
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}
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SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
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@ -236,6 +236,10 @@ namespace llvm {
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SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
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SelectionDAG &DAG);
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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@ -4047,6 +4047,51 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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// isLegalAddressingMode - Return true if the addressing mode represented
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// by AM is legal for this target, for a load/store of the specified type.
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bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const {
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// X86 supports extremely general addressing modes.
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// X86 allows a sign-extended 32-bit immediate field as a displacement.
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if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
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return false;
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if (AM.BaseGV) {
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// X86-64 only supports addr of globals in small code model.
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if (Subtarget->is64Bit() &&
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getTargetMachine().getCodeModel() != CodeModel::Small)
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return false;
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// We can only fold this if we don't need a load either.
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if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
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return false;
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}
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switch (AM.Scale) {
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case 0:
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case 1:
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case 2:
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case 4:
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case 8:
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// These scales always work.
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break;
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case 3:
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case 5:
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case 9:
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// These scales are formed with basereg+scalereg. Only accept if there is
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// no basereg yet.
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if (AM.HasBaseReg)
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return false;
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break;
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default: // Other stuff never works.
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return false;
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}
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return true;
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}
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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@ -335,6 +335,10 @@ namespace llvm {
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode for load / store of the
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/// given type.
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