6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-02 04:24:22 +00:00
Code Issues Projects Releases Wiki Activity

[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2014-03-01 01:04:26 +00:00
parent 5de5680689
commit c9bf74fdc5
6 changed files with 23 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
View File

@ -20,6 +20,14 @@
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
// namespace. But SPARC backend uses "SP" as its namespace.
namespace llvm {
namespace Sparc {
using namespace SP;
}
}
#define GET_INSTRUCTION_NAME #define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "SparcGenAsmWriter.inc" #include "SparcGenAsmWriter.inc"

3
lib/Target/Sparc/SparcInstrAliases.td
View File

@ -140,3 +140,6 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
// mov simm13, rd -> or %g0, simm13, rd // mov simm13, rd -> or %g0, simm13, rd
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
// restore -> restore %g0, %g0, %g0
def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;

3
test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
View File

@ -21,7 +21,8 @@ entry:
;SPARC64: save %sp, -128, %sp ;SPARC64: save %sp, -128, %sp
;SPARC64: add %fp, 2047, %i0 ;SPARC64: add %fp, 2047, %i0
;SPARC64: ret ;SPARC64: ret
;SPARC64: restore %g0, %g0, %g0 ;SPARC64-NOT: restore %g0, %g0, %g0
;SPARC64: restore
%0 = tail call i8* @llvm.frameaddress(i32 0) %0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0 ret i8* %0

6
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
View File

@ -141,7 +141,8 @@ entry:
;CHECK-LABEL: restore_or_imm: ;CHECK-LABEL: restore_or_imm:
;CHECK: or %o0, 20, %i0 ;CHECK: or %o0, 20, %i0
;CHECK: ret ;CHECK: ret
;CHECK: restore %g0, %g0, %g0 ;CHECK-NOT: restore %g0, %g0, %g0
;CHECK: restore
%0 = tail call i32 @bar(i32 %a) nounwind %0 = tail call i32 @bar(i32 %a) nounwind
%1 = or i32 %0, 20 %1 = or i32 %0, 20
ret i32 %1 ret i32 %1
@ -174,7 +175,8 @@ define i32 @restore_sethi_large(i32 %a) {
entry: entry:
;CHECK-LABEL: restore_sethi_large: ;CHECK-LABEL: restore_sethi_large:
;CHECK: sethi 4000, %i0 ;CHECK: sethi 4000, %i0
;CHECK: restore %g0, %g0, %g0 ;CHECK-NOT: restore %g0, %g0, %g0
;CHECK: restore
%0 = tail call i32 @bar(i32 %a) nounwind %0 = tail call i32 @bar(i32 %a) nounwind
%1 = icmp ne i32 %0, 0 %1 = icmp ne i32 %0, 0
%2 = select i1 %1, i32 4096000, i32 0 %2 = select i1 %1, i32 4096000, i32 0

3
test/MC/Disassembler/Sparc/sparc.txt
View File

@ -167,3 +167,6 @@
# CHECK: fbo 4194303 # CHECK: fbo 4194303
0x1f 0xbf 0xff 0xff 0x1f 0xbf 0xff 0xff
# CHECK: restore
0x81 0xe8 0x00 0x00

3
test/MC/Sparc/sparc-alu-instructions.s
View File

@ -75,3 +75,6 @@
! CHECK: or %g0, 255, %g3 ! encoding: [0x86,0x10,0x20,0xff] ! CHECK: or %g0, 255, %g3 ! encoding: [0x86,0x10,0x20,0xff]
mov 0xff, %g3 mov 0xff, %g3
! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00]
restore %g0, %g0, %g0