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Add missing register forms of instructions to the ARM CMP-folding code. This

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fixes <rdar://problem/9287901>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-04-15 20:28:28 +00:00
parent 99a2e98edd
commit ca3f6a3925
2 changed files with 34 additions and 0 deletions
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12
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1618,16 +1618,26 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
// Set the "zero" bit in CPSR.
switch (MI->getOpcode()) {
default: break;
case ARM::RSBrr:
case ARM::RSBri:
case ARM::RSCrr:
case ARM::RSCri:
case ARM::ADDrr:
case ARM::ADDri:
case ARM::ADCrr:
case ARM::ADCri:
case ARM::SUBrr:
case ARM::SUBri:
case ARM::SBCrr:
case ARM::SBCri:
case ARM::t2RSBri:
case ARM::t2ADDrr:
case ARM::t2ADDri:
case ARM::t2ADCrr:
case ARM::t2ADCri:
case ARM::t2SUBrr:
case ARM::t2SUBri:
case ARM::t2SBCrr:
case ARM::t2SBCri: {
// Scan forward for the use of CPSR, if it's a conditional code requires
// checking of V bit, then this is not safe to do. If we can't find the
@ -1669,7 +1679,9 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
// fallthrough
}
case ARM::ANDrr:
case ARM::ANDri:
case ARM::t2ANDrr:
case ARM::t2ANDri:
// Toggle the optional operand to CPSR.
MI->getOperand(5).setReg(ARM::CPSR);

22
test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
; CHECK: _f
; CHECK: adds
; CHECK-NOT: cmp
; CHECK: blxeq _g
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
%add = add nsw i32 %b, %a
%cmp = icmp eq i32 %add, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void (...)* @g(i32 %a, i32 %b) nounwind
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 %add
}
declare void @g(...)