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https://github.com/c64scene-ar/llvm-6502.git
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* Tabs to spaces
* Send an error message to std::cerr before abort()ing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
a1d90eb7bf
commit
ca428df792
@ -32,64 +32,65 @@ PowerPCRegisterInfo::PowerPCRegisterInfo()
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PPC32::ADJCALLSTACKUP) {}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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if (RC == PowerPC::GPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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}
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}
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else if (RC == PowerPC::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 3;
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case 8: return 4;
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}
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}
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abort();
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if (RC == PowerPC::GPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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}
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} else if (RC == PowerPC::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 3;
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case 8: return 4;
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}
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}
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std::cerr << "Invalid register class to getIdx()!\n";
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abort();
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}
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int PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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int
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PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD };
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unsigned OC = Opcode[getIdx(RC)];
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MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
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return 1;
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static const unsigned Opcode[] = {
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PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
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return 1;
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}
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int PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const{
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static const unsigned Opcode[] =
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{ PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD };
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unsigned OC = Opcode[getIdx(RC)];
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MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
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return 1;
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static const unsigned Opcode[] = {
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PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
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return 1;
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}
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int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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MachineInstr *I;
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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MachineInstr *I;
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if(RC == PowerPC::GPRCRegisterClass) {
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I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PowerPC::FPRCRegisterClass) {
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I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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MBB.insert(MI, I);
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return 1;
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if (RC == PowerPC::GPRCRegisterClass) {
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I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PowerPC::FPRCRegisterClass) {
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I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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MBB.insert(MI, I);
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return 1;
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}
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//===----------------------------------------------------------------------===//
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@ -101,7 +102,7 @@ int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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void PowerPCRegisterInfo::
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@ -121,10 +122,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr *New;
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if (Old->getOpcode() == PPC32::ADJCALLSTACKDOWN) {
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New=BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1).addSImm(-Amount);
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New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
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.addSImm(-Amount);
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} else {
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assert(Old->getOpcode() == PPC32::ADJCALLSTACKUP);
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New=BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1).addSImm(Amount);
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New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
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.addSImm(Amount);
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}
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// Replace the pseudo instruction with a new instruction...
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@ -166,99 +169,97 @@ PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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}
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void PowerPCRegisterInfo::processFunctionBeforeFrameFinalized(
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MachineFunction &MF) const {
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// Do Nothing
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void
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PowerPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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const {
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// Do Nothing
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}
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void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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if (MFI->hasCalls()) {
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// When we have no frame pointer, we reserve argument space for call sites
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// in the function immediately on entry to the current function. This
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// eliminates the need for add/sub brackets around call sites.
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//
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NumBytes += MFI->getMaxCallFrameSize();
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// Round the size to a multiple of the alignment (don't forget the 4 byte
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// offset though).
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
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if (MFI->hasCalls()) {
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// When we have no frame pointer, we reserve argument space for call sites
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// in the function immediately on entry to the current function. This
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// eliminates the need for add/sub brackets around call sites.
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//
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NumBytes += MFI->getMaxCallFrameSize();
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// Round the size to a multiple of the alignment (don't forget the 4 byte
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// offset though).
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
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// Store the incoming LR so it is preserved across calls
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MI= BuildMI(PPC32::MovePCtoLR, 0, PPC32::LR).addReg(PPC32::LR);
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MBB.insert(MBBI, MI);
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MI= BuildMI(PPC32::MFSPR, 1, PPC32::R0).addImm(8);
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MBB.insert(MBBI, MI);
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MI= BuildMI(PPC32::STW, 3).addReg(PPC32::R0).addSImm(8).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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}
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r1 -= numbytes
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if (NumBytes) {
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MI= BuildMI(PPC32::STWU, 2, PPC32::R1).addImm(-NumBytes).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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}
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// Store the incoming LR so it is preserved across calls
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MI = BuildMI(PPC32::MovePCtoLR, 0, PPC32::LR).addReg(PPC32::LR);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::MFSPR, 1, PPC32::R0).addImm(8);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::STW, 3).addReg(PPC32::R0).addSImm(8).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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}
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r1 -= numbytes
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if (NumBytes) {
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MI = BuildMI(PPC32::STWU, 2, PPC32::R1).addImm(-NumBytes).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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}
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}
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void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == PPC32::BLR &&
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"Can only insert epilog into returning blocks");
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == PPC32::BLR &&
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"Can only insert epilog into returning blocks");
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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// adjust stack pointer back: r1 += numbytes
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if (NumBytes) {
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MI =BuildMI(PPC32::ADDI, 2, PPC32::R1)
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.addReg(PPC32::R1)
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.addSImm(NumBytes);
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MBB.insert(MBBI, MI);
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}
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// If we have calls, restore the LR value before we branch to it
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if (MFI->hasCalls()) {
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MI = BuildMI(PPC32::LWZ, 2, PPC32::R0).addSImm(8).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0);
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MBB.insert(MBBI, MI);
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}
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// adjust stack pointer back: r1 += numbytes
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if (NumBytes) {
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MI =BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1).addSImm(NumBytes);
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MBB.insert(MBBI, MI);
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}
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// If we have calls, restore the LR value before we branch to it
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if (MFI->hasCalls()) {
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MI = BuildMI(PPC32::LWZ, 2, PPC32::R0).addSImm(8).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0);
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MBB.insert(MBBI, MI);
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}
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}
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#include "PowerPCGenRegisterInfo.inc"
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const TargetRegisterClass*
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PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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switch (Ty->getTypeID()) {
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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}
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