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ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -71,13 +71,14 @@ def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
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"ARM v6m",
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[FeatureDB]>;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2">;
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"ARM v6t2",
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[FeatureThumb2]>;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A",
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[FeatureDB]>;
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[FeatureThumb2, FeatureNEON, FeatureDB]>;
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def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
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"ARM v7M",
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[FeatureDB]>;
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[FeatureThumb2, FeatureDB]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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@ -139,21 +140,19 @@ def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
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def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries,
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[ArchV6T2, FeatureThumb2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries,
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[ArchV6T2, FeatureThumb2, FeatureVFP2]>;
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
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[ArchV7A, FeatureHasSlowVMLx,
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FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2XtPk]>;
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[ArchV7A, FeatureT2XtPk]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
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def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
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def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureHWDiv]>;
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def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureHWDiv]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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