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[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:44:44 +00:00
parent 19b573d9c9
commit cb9ca905e3
3 changed files with 24 additions and 4 deletions
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18
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -1417,13 +1417,17 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case ARM64::ADDXrx64:
case ARM64::ADDSXrx64:
case ARM64::SUBXrx64:
case ARM64::SUBSXrx64:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
case ARM64::SUBSXrx64:
case ARM64::ADDSXrx64:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
Inst.addOperand(MCOperand::CreateImm(extend));
@@ -1439,13 +1443,19 @@ static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
unsigned imm;
if (Datasize) {
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
if (Inst.getOpcode() == ARM64::ANDSXri)
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 13);
if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
return Fail;
} else {
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
if (Inst.getOpcode() == ARM64::ANDSWri)
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 12);
if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))