6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Fix an incorrectly inverted condition.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31773 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-11-16 00:08:20 +00:00
parent dbf58837c4
commit cc47021f49
2 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2856,7 +2856,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
} else
return false;
if (!Ptr.Val->hasOneUse())
if (Ptr.Val->hasOneUse())
return false;
for (SDNode::use_iterator I = Ptr.Val->use_begin(),

1
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1481,7 +1481,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// Perform various simplifications.
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
//ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
switch (Opcode) {
case ISD::SETCC: {
// Use FoldSetCC to simplify SETCC's.