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ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.

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As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2013-09-27 13:28:17 +00:00
parent 9f30d43122
commit cca1146119
3 changed files with 50 additions and 21 deletions
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11
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5347,8 +5347,17 @@ validateInstruction(MCInst &Inst,
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST: {
unsigned RtReg = Inst.getOperand(0).getReg();
// Rt can't be R14.
if (RtReg == ARM::LR)
return Error(Operands[3]->getStartLoc(),
"Rt can't be R14");
unsigned Rt = MRI->getEncodingValue(RtReg);
// Rt must be even-numbered.
if ((Rt & 1) == 1)
return Error(Operands[3]->getStartLoc(),
"Rt must be even-numbered");
// Rt2 must be Rt + 1.
unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
if (Rt2 != Rt + 1)
return Error(Operands[3]->getStartLoc(),

20
test/MC/ARM/arm-ldrd.s Normal file
View File

@ -0,0 +1,20 @@
// RUN: not llvm-mc -arch arm -mattr=+v5te \
// RUN: < %s >/dev/null 2> %t
// RUN: grep "error: Rt must be even-numbered" %t | count 7
// RUN: grep "error: Rt can't be R14" %t | count 7
// rdar://14479793
ldrd r1, r2, [pc, #0]
ldrd lr, pc, [pc, #0]
ldrd r1, r2, [r3, #4]
ldrd lr, pc, [r3, #4]
ldrd r1, r2, [r3], #4
ldrd lr, pc, [r3], #4
ldrd r1, r2, [r3, #4]!
ldrd lr, pc, [r3, #4]!
ldrd r1, r2, [r3, -r4]!
ldrd lr, pc, [r3, -r4]!
ldrd r1, r2, [r3, r4]
ldrd lr, pc, [r3, r4]
ldrd r1, r2, [r3], r4
ldrd lr, pc, [r3], r4

40
test/MC/ARM/arm-memory-instructions.s
View File

@ -114,21 +114,21 @@ _func:
@------------------------------------------------------------------------------
@ LDRD (immediate)
@------------------------------------------------------------------------------
ldrd r3, r4, [r5]
ldrd r7, r8, [r2, #15]
ldrd r1, r2, [r9, #32]!
ldrd r2, r3, [r5]
ldrd r6, r7, [r2, #15]
ldrd r0, r1, [r9, #32]!
ldrd r6, r7, [r1], #8
ldrd r1, r2, [r8], #0
ldrd r1, r2, [r8], #+0
ldrd r1, r2, [r8], #-0
ldrd r0, r1, [r8], #0
ldrd r0, r1, [r8], #+0
ldrd r0, r1, [r8], #-0
@ CHECK: ldrd r3, r4, [r5] @ encoding: [0xd0,0x30,0xc5,0xe1]
@ CHECK: ldrd r7, r8, [r2, #15] @ encoding: [0xdf,0x70,0xc2,0xe1]
@ CHECK: ldrd r1, r2, [r9, #32]! @ encoding: [0xd0,0x12,0xe9,0xe1]
@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0]
@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0]
@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0]
@ CHECK: ldrd r1, r2, [r8], #-0 @ encoding: [0xd0,0x10,0x48,0xe0]
@ CHECK: ldrd r2, r3, [r5] @ encoding: [0xd0,0x20,0xc5,0xe1]
@ CHECK: ldrd r6, r7, [r2, #15] @ encoding: [0xdf,0x60,0xc2,0xe1]
@ CHECK: ldrd r0, r1, [r9, #32]! @ encoding: [0xd0,0x02,0xe9,0xe1]
@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0]
@ CHECK: ldrd r0, r1, [r8], #0 @ encoding: [0xd0,0x00,0xc8,0xe0]
@ CHECK: ldrd r0, r1, [r8], #0 @ encoding: [0xd0,0x00,0xc8,0xe0]
@ CHECK: ldrd r0, r1, [r8], #-0 @ encoding: [0xd0,0x00,0x48,0xe0]
@------------------------------------------------------------------------------
@ -143,15 +143,15 @@ Lbaz: .quad 0
@------------------------------------------------------------------------------
@ LDRD (register)
@------------------------------------------------------------------------------
ldrd r3, r4, [r1, r3]
ldrd r4, r5, [r1, r3]
ldrd r4, r5, [r7, r2]!
ldrd r1, r2, [r8], r12
ldrd r1, r2, [r8], -r12
ldrd r0, r1, [r8], r12
ldrd r0, r1, [r8], -r12
@ CHECK: ldrd r3, r4, [r1, r3] @ encoding: [0xd3,0x30,0x81,0xe1]
@ CHECK: ldrd r4, r5, [r7, r2]! @ encoding: [0xd2,0x40,0xa7,0xe1]
@ CHECK: ldrd r1, r2, [r8], r12 @ encoding: [0xdc,0x10,0x88,0xe0]
@ CHECK: ldrd r1, r2, [r8], -r12 @ encoding: [0xdc,0x10,0x08,0xe0]
@ CHECK: ldrd r4, r5, [r1, r3] @ encoding: [0xd3,0x40,0x81,0xe1]
@ CHECK: ldrd r4, r5, [r7, r2]! @ encoding: [0xd2,0x40,0xa7,0xe1]
@ CHECK: ldrd r0, r1, [r8], r12 @ encoding: [0xdc,0x00,0x88,0xe0]
@ CHECK: ldrd r0, r1, [r8], -r12 @ encoding: [0xdc,0x00,0x08,0xe0]
@------------------------------------------------------------------------------