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Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -519,12 +519,9 @@ static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
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}
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}
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/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
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/// returns true if the operands should be inverted to form the proper
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/// comparison.
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static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
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/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
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static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
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ARMCC::CondCodes &CondCode2) {
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bool Invert = false;
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CondCode2 = ARMCC::AL;
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switch (CC) {
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default: llvm_unreachable("Unknown FP condition!");
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@ -535,7 +532,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
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case ISD::SETGE:
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case ISD::SETOGE: CondCode = ARMCC::GE; break;
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case ISD::SETOLT: CondCode = ARMCC::MI; break;
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case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
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case ISD::SETOLE: CondCode = ARMCC::LS; break;
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case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
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case ISD::SETO: CondCode = ARMCC::VC; break;
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case ISD::SETUO: CondCode = ARMCC::VS; break;
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@ -549,7 +546,6 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
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case ISD::SETNE:
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case ISD::SETUNE: CondCode = ARMCC::NE; break;
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}
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return Invert;
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}
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//===----------------------------------------------------------------------===//
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@ -1814,8 +1810,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
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}
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ARMCC::CondCodes CondCode, CondCode2;
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if (FPCCToARMCC(CC, CondCode, CondCode2))
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std::swap(TrueVal, FalseVal);
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FPCCToARMCC(CC, CondCode, CondCode2);
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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@ -1851,9 +1846,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
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assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
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ARMCC::CondCodes CondCode, CondCode2;
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if (FPCCToARMCC(CC, CondCode, CondCode2))
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// Swap the LHS/RHS of the comparison if needed.
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std::swap(LHS, RHS);
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FPCCToARMCC(CC, CondCode, CondCode2);
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SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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18
test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
Normal file
18
test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc -O1 -march=arm -mattr=+vfp2 < %s | FileCheck %s
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; pr4939
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define void @test(double* %x, double* %y) nounwind {
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%1 = load double* %x, align 4
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%2 = load double* %y, align 4
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%3 = fsub double -0.000000e+00, %1
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%4 = fcmp ugt double %2, %3
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br i1 %4, label %bb1, label %bb2
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bb1:
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;CHECK: fstdhi
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store double %1, double* %y, align 4
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br label %bb2
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bb2:
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ret void
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}
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