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Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.

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See the bug report for details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-09-09 23:14:54 +00:00
parent c5ea263a23
commit cd3b9a4f17
2 changed files with 23 additions and 12 deletions
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17
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -519,12 +519,9 @@ static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
}
}
/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
/// returns true if the operands should be inverted to form the proper
/// comparison.
static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
ARMCC::CondCodes &CondCode2) {
bool Invert = false;
CondCode2 = ARMCC::AL;
switch (CC) {
default: llvm_unreachable("Unknown FP condition!");
@ -535,7 +532,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
case ISD::SETGE:
case ISD::SETOGE: CondCode = ARMCC::GE; break;
case ISD::SETOLT: CondCode = ARMCC::MI; break;
case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
case ISD::SETOLE: CondCode = ARMCC::LS; break;
case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
case ISD::SETO: CondCode = ARMCC::VC; break;
case ISD::SETUO: CondCode = ARMCC::VS; break;
@ -549,7 +546,6 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
case ISD::SETNE:
case ISD::SETUNE: CondCode = ARMCC::NE; break;
}
return Invert;
}
//===----------------------------------------------------------------------===//
@ -1814,8 +1810,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
}
ARMCC::CondCodes CondCode, CondCode2;
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
FPCCToARMCC(CC, CondCode, CondCode2);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
@ -1851,9 +1846,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
ARMCC::CondCodes CondCode, CondCode2;
if (FPCCToARMCC(CC, CondCode, CondCode2))
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
FPCCToARMCC(CC, CondCode, CondCode2);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);

18
test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc -O1 -march=arm -mattr=+vfp2 < %s | FileCheck %s
; pr4939
define void @test(double* %x, double* %y) nounwind {
%1 = load double* %x, align 4
%2 = load double* %y, align 4
%3 = fsub double -0.000000e+00, %1
%4 = fcmp ugt double %2, %3
br i1 %4, label %bb1, label %bb2
bb1:
;CHECK: fstdhi
store double %1, double* %y, align 4
br label %bb2
bb2:
ret void
}