6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-27 14:24:40 +00:00
Code Issues Projects Releases Wiki Activity

Replace a few uses of SelectionDAG::getTargetNode with

Browse Source 
SelectionDAG::SelectNodeTo in the instruction selector. This
updates existing nodes in place instead of creating new ones.

Go back to selecting ISD::DBG_LABEL nodes into
TargetInstrInfo::DBG_LABEL nodes instead of leaving them
unselected, now that SelectNodeTo allows us to update them
in place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2008-07-02 23:23:19 +00:00
parent 501e763dfe
commit cd920d9ecf
4 changed files with 83 additions and 123 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -885,16 +885,6 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
assert(0 && "EntryToken should have been excluded from the schedule!");
break;
case ISD::TokenFactor: // fall thru
case ISD::DECLARE:
case ISD::SRCVALUE:
break;
case ISD::DBG_LABEL:
BB->push_back(BuildMI(TII->get(TargetInstrInfo::DBG_LABEL))
.addImm(cast<LabelSDNode>(Node)->getLabelID()));
break;
case ISD::EH_LABEL:
BB->push_back(BuildMI(TII->get(TargetInstrInfo::EH_LABEL))
.addImm(cast<LabelSDNode>(Node)->getLabelID()));
break;
case ISD::CopyToReg: {
unsigned SrcReg;
@ -951,34 +941,14 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
switch (Flags & 7) {
default: assert(0 && "Bad flags!");
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addOperand(MachineOperand::CreateReg(Reg, false));
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addOperand(MachineOperand::CreateReg(Reg, true));
}
break;
case 3: { // Immediate.
for (; NumVals; --NumVals, ++i) {
if (ConstantSDNode *CS =
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
} else if (GlobalAddressSDNode *GA =
dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
GA->getOffset()));
} else {
BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
}
}
break;
}
case 1: // Use of register.
case 3: // Immediate.
case 4: // Addressing mode.
// The addressing mode has been selected, just add all of the
// operands to the machine instruction.