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Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and
MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161090 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13,6 +13,7 @@ tablegen(LLVM MipsGenEDInfo.inc -gen-enhanced-disassembly-info)
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add_public_tablegen_target(MipsCommonTableGen)
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add_llvm_target(MipsCodeGen
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Mips16FrameLowering.cpp
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Mips16InstrInfo.cpp
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MipsAnalyzeImmediate.cpp
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MipsAsmPrinter.cpp
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@ -27,6 +28,7 @@ add_llvm_target(MipsCodeGen
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MipsMCInstLower.cpp
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MipsMachineFunction.cpp
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MipsRegisterInfo.cpp
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MipsSEFrameLowering.cpp
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MipsSEInstrInfo.cpp
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MipsSubtarget.cpp
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MipsTargetMachine.cpp
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82
lib/Target/Mips/Mips16FrameLowering.cpp
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82
lib/Target/Mips/Mips16FrameLowering.cpp
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@ -0,0 +1,82 @@
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//===-- Mips16FrameLowering.cpp - Mips16 Frame Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16FrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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uint64_t StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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// Adjust stack.
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if (isInt<16>(-StackSize))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
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}
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void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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uint64_t StackSize = MFI->getStackSize();
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if (!StackSize)
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return;
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// Adjust stack.
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if (isInt<16>(StackSize))
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// assumes stacksize multiple of 8
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BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
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}
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bool Mips16FrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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// FIXME: implement.
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return true;
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}
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bool
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Mips16FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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// FIXME: implement.
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return true;
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}
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void Mips16FrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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}
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43
lib/Target/Mips/Mips16FrameLowering.h
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43
lib/Target/Mips/Mips16FrameLowering.h
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//===-- Mips16FrameLowering.h - Mips16 frame lowering ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPS16_FRAMEINFO_H
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#define MIPS16_FRAMEINFO_H
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#include "MipsFrameLowering.h"
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namespace llvm {
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class Mips16FrameLowering : public MipsFrameLowering {
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public:
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explicit Mips16FrameLowering(const MipsSubtarget &STI)
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: MipsFrameLowering(STI) {}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const;
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};
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} // End llvm namespace
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#endif
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@ -89,204 +89,3 @@ bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// First, compute final stack size.
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uint64_t StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack.
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if (isInt<16>(-StackSize)) {// addi sp, sp, (-stacksize)
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if (STI.inMips16Mode())
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BuildMI(MBB, MBBI, dl,
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TII.get(Mips::SaveRaF16)).addImm(StackSize); // cleanup
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else
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
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}
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else { // Expand immediate that doesn't fit in 16-bit.
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unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
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MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
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Mips::loadImmediate(-StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
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0);
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
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}
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
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DstML = MachineLocation(MachineLocation::VirtualFP);
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SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegClass.contains(Reg)) {
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MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
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MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
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MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
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MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
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if (!STI.isLittle())
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std::swap(SrcML0, SrcML1);
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Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
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Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
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} else {
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// Reg is either in CPURegs or FGR32.
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(Reg);
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Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
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}
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
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// emit ".cfi_def_cfa_register $fp"
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MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
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DstML = MachineLocation(FP);
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SrcML = MachineLocation(MachineLocation::VirtualFP);
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Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
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}
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}
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void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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}
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// Get the number of bytes from FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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if (!StackSize)
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return;
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// Adjust stack.
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if (isInt<16>(StackSize)) { // addi sp, sp, (-stacksize)
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if (STI.inMips16Mode())
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// assumes stacksize multiple of 8
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BuildMI(MBB, MBBI, dl,
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TII.get(Mips::RestoreRaF16)).addImm(StackSize);
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else
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
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}
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else { // Expand immediate that doesn't fit in 16-bit.
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unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
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MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
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Mips::loadImmediate(StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
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0);
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
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}
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}
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void MipsFrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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// FIXME: remove this code if register allocator can correctly mark
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// $fp and $ra used or unused.
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// Mark $fp and $ra as used or unused.
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if (hasFP(MF))
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MRI.setPhysRegUsed(FP);
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}
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bool MipsFrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineBasicBlock *EntryBlock = MF->begin();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[i].getReg();
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bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
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&& MF->getFrameInfo()->isReturnAddressTaken();
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if (!IsRAAndRetAddrIsTaken)
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EntryBlock->addLiveIn(Reg);
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// Insert the spill to the stack frame.
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bool IsKill = !IsRAAndRetAddrIsTaken;
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
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CSI[i].getFrameIdx(), RC, TRI);
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}
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return true;
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}
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@ -31,20 +31,7 @@ public:
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STI(sti) {
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}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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bool hasFP(const MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const;
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};
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} // End llvm namespace
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225
lib/Target/Mips/MipsSEFrameLowering.cpp
Normal file
225
lib/Target/Mips/MipsSEFrameLowering.cpp
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//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEFrameLowering.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
||||
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
||||
unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
|
||||
unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
||||
unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
|
||||
|
||||
// First, compute final stack size.
|
||||
uint64_t StackSize = MFI->getStackSize();
|
||||
|
||||
// No need to allocate space on the stack.
|
||||
if (StackSize == 0 && !MFI->adjustsStack()) return;
|
||||
|
||||
MachineModuleInfo &MMI = MF.getMMI();
|
||||
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
|
||||
MachineLocation DstML, SrcML;
|
||||
|
||||
// Adjust stack.
|
||||
if (isInt<16>(-StackSize))// addi sp, sp, (-stacksize)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
|
||||
else { // Expand immediate that doesn't fit in 16-bit.
|
||||
unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
|
||||
|
||||
MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
|
||||
Mips::loadImmediate(-StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
|
||||
0);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
|
||||
}
|
||||
|
||||
// emit ".cfi_def_cfa_offset StackSize"
|
||||
MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
|
||||
BuildMI(MBB, MBBI, dl,
|
||||
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
|
||||
DstML = MachineLocation(MachineLocation::VirtualFP);
|
||||
SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
|
||||
Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
|
||||
|
||||
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
||||
|
||||
if (CSI.size()) {
|
||||
// Find the instruction past the last instruction that saves a callee-saved
|
||||
// register to the stack.
|
||||
for (unsigned i = 0; i < CSI.size(); ++i)
|
||||
++MBBI;
|
||||
|
||||
// Iterate over list of callee-saved registers and emit .cfi_offset
|
||||
// directives.
|
||||
MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
|
||||
BuildMI(MBB, MBBI, dl,
|
||||
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
|
||||
|
||||
for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
|
||||
E = CSI.end(); I != E; ++I) {
|
||||
int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
|
||||
unsigned Reg = I->getReg();
|
||||
|
||||
// If Reg is a double precision register, emit two cfa_offsets,
|
||||
// one for each of the paired single precision registers.
|
||||
if (Mips::AFGR64RegClass.contains(Reg)) {
|
||||
MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
|
||||
MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
|
||||
MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
|
||||
MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
|
||||
|
||||
if (!STI.isLittle())
|
||||
std::swap(SrcML0, SrcML1);
|
||||
|
||||
Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
|
||||
Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
|
||||
} else {
|
||||
// Reg is either in CPURegs or FGR32.
|
||||
DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
|
||||
SrcML = MachineLocation(Reg);
|
||||
Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// if framepointer enabled, set it to point to the stack pointer.
|
||||
if (hasFP(MF)) {
|
||||
// Insert instruction "move $fp, $sp" at this location.
|
||||
BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
|
||||
|
||||
// emit ".cfi_def_cfa_register $fp"
|
||||
MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
|
||||
BuildMI(MBB, MBBI, dl,
|
||||
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
|
||||
DstML = MachineLocation(FP);
|
||||
SrcML = MachineLocation(MachineLocation::VirtualFP);
|
||||
Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
|
||||
}
|
||||
}
|
||||
|
||||
void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const {
|
||||
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
const MipsInstrInfo &TII =
|
||||
*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
|
||||
DebugLoc dl = MBBI->getDebugLoc();
|
||||
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
||||
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
||||
unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
|
||||
unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
||||
unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
|
||||
|
||||
// if framepointer enabled, restore the stack pointer.
|
||||
if (hasFP(MF)) {
|
||||
// Find the first instruction that restores a callee-saved register.
|
||||
MachineBasicBlock::iterator I = MBBI;
|
||||
|
||||
for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
|
||||
--I;
|
||||
|
||||
// Insert instruction "move $sp, $fp" at this location.
|
||||
BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
|
||||
}
|
||||
|
||||
// Get the number of bytes from FrameInfo
|
||||
uint64_t StackSize = MFI->getStackSize();
|
||||
|
||||
if (!StackSize)
|
||||
return;
|
||||
|
||||
// Adjust stack.
|
||||
if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
|
||||
else { // Expand immediate that doesn't fit in 16-bit.
|
||||
unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
|
||||
|
||||
MF.getInfo<MipsFunctionInfo>()->setEmitNOAT();
|
||||
Mips::loadImmediate(StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl, false,
|
||||
0);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(ADDu), SP).addReg(SP).addReg(ATReg);
|
||||
}
|
||||
}
|
||||
|
||||
bool MipsSEFrameLowering::
|
||||
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const {
|
||||
MachineFunction *MF = MBB.getParent();
|
||||
MachineBasicBlock *EntryBlock = MF->begin();
|
||||
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
|
||||
|
||||
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
||||
// Add the callee-saved register as live-in. Do not add if the register is
|
||||
// RA and return address is taken, because it has already been added in
|
||||
// method MipsTargetLowering::LowerRETURNADDR.
|
||||
// It's killed at the spill, unless the register is RA and return address
|
||||
// is taken.
|
||||
unsigned Reg = CSI[i].getReg();
|
||||
bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
|
||||
&& MF->getFrameInfo()->isReturnAddressTaken();
|
||||
if (!IsRAAndRetAddrIsTaken)
|
||||
EntryBlock->addLiveIn(Reg);
|
||||
|
||||
// Insert the spill to the stack frame.
|
||||
bool IsKill = !IsRAAndRetAddrIsTaken;
|
||||
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
||||
TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
|
||||
CSI[i].getFrameIdx(), RC, TRI);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
||||
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
|
||||
// Reserve call frame if the size of the maximum call frame fits into 16-bit
|
||||
// immediate field and there are no variable sized objects on the stack.
|
||||
return isInt<16>(MFI->getMaxCallFrameSize()) && !MFI->hasVarSizedObjects();
|
||||
}
|
||||
|
||||
void MipsSEFrameLowering::
|
||||
processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
||||
RegScavenger *RS) const {
|
||||
MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
||||
|
||||
// Mark $fp as used if function has dedicated frame pointer.
|
||||
if (hasFP(MF))
|
||||
MRI.setPhysRegUsed(FP);
|
||||
}
|
44
lib/Target/Mips/MipsSEFrameLowering.h
Normal file
44
lib/Target/Mips/MipsSEFrameLowering.h
Normal file
@ -0,0 +1,44 @@
|
||||
//===-- MipsSEFrameLowering.h - Mips32/64 frame lowering --------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef MIPSSE_FRAMEINFO_H
|
||||
#define MIPSSE_FRAMEINFO_H
|
||||
|
||||
#include "MipsFrameLowering.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MipsSEFrameLowering : public MipsFrameLowering {
|
||||
public:
|
||||
explicit MipsSEFrameLowering(const MipsSubtarget &STI)
|
||||
: MipsFrameLowering(STI) {}
|
||||
|
||||
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
|
||||
/// the function.
|
||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
|
||||
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const;
|
||||
|
||||
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
||||
RegScavenger *RS) const;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
@ -12,9 +12,11 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsSEInstrInfo.h"
|
||||
#include "Mips16InstrInfo.h"
|
||||
#include "Mips.h"
|
||||
#include "Mips16FrameLowering.h"
|
||||
#include "Mips16InstrInfo.h"
|
||||
#include "MipsSEFrameLowering.h"
|
||||
#include "MipsSEInstrInfo.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
@ -39,6 +41,18 @@ static const MipsInstrInfo *genInstrInfo(MipsTargetMachine &TM) {
|
||||
return II;
|
||||
}
|
||||
|
||||
static const MipsFrameLowering *genFrameLowering(MipsTargetMachine &TM,
|
||||
const MipsSubtarget &ST) {
|
||||
const MipsFrameLowering *FL;
|
||||
|
||||
if (TM.getSubtargetImpl()->inMips16Mode())
|
||||
FL = new Mips16FrameLowering(ST);
|
||||
else
|
||||
FL = new MipsSEFrameLowering(ST);
|
||||
|
||||
return FL;
|
||||
}
|
||||
|
||||
// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
|
||||
// The stack is always 8 byte aligned
|
||||
// On function prologue, the stack is created by decrementing
|
||||
@ -62,7 +76,7 @@ MipsTargetMachine(const Target &T, StringRef TT,
|
||||
"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
|
||||
"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
|
||||
InstrInfo(genInstrInfo(*this)),
|
||||
FrameLowering(Subtarget),
|
||||
FrameLowering(genFrameLowering(*this, Subtarget)),
|
||||
TLInfo(*this), TSInfo(*this), JITInfo() {
|
||||
}
|
||||
|
||||
|
@ -32,7 +32,7 @@ class MipsTargetMachine : public LLVMTargetMachine {
|
||||
MipsSubtarget Subtarget;
|
||||
const TargetData DataLayout; // Calculates type size & alignment
|
||||
const MipsInstrInfo *InstrInfo;
|
||||
MipsFrameLowering FrameLowering;
|
||||
const MipsFrameLowering *FrameLowering;
|
||||
MipsTargetLowering TLInfo;
|
||||
MipsSelectionDAGInfo TSInfo;
|
||||
MipsJITInfo JITInfo;
|
||||
@ -49,7 +49,7 @@ public:
|
||||
virtual const MipsInstrInfo *getInstrInfo() const
|
||||
{ return InstrInfo; }
|
||||
virtual const TargetFrameLowering *getFrameLowering() const
|
||||
{ return &FrameLowering; }
|
||||
{ return FrameLowering; }
|
||||
virtual const MipsSubtarget *getSubtargetImpl() const
|
||||
{ return &Subtarget; }
|
||||
virtual const TargetData *getTargetData() const
|
||||
|
@ -6,7 +6,7 @@
|
||||
|
||||
define void @f() nounwind {
|
||||
entry:
|
||||
; CHECK: lui $at, 65534
|
||||
; CHECK: lui $at, 65535
|
||||
; CHECK: addiu $at, $at, -16
|
||||
; CHECK: addu $sp, $sp, $at
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user