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[x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous

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to the zero-extend-vector-inreg node introduced previously for the same
purpose: manage the type legalization of widened extend operations,
especially to support the experimental widening mode for x86.

I'm adding both because sign-extend is expanded in terms of any-extend
with shifts to propagate the sign bit. This removes the last
fundamental scalarization from vec_cast2.ll (a test case that hit many
really bad edge cases for widening legalization), although the trunc
tests in that file still appear scalarized because the the shuffle
legalization is scalarizing. Funny thing, I've been working on that.

Some initial experiments with this and SSE2 scenarios is showing
moderately good behavior already for sign extension. Still some work to
do on the shuffle combining on X86 before we're generating optimal
sequences, but avoiding scalarization is a huge step forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-07-10 12:32:32 +00:00
parent 35dda8a53c
commit cdbdfa28d1
9 changed files with 165 additions and 9 deletions
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22
include/llvm/CodeGen/ISDOpcodes.h
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@ -379,6 +379,28 @@ namespace ISD {
/// operand, a ValueType node.
SIGN_EXTEND_INREG,
/// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
/// in-register any-extension of the low lanes of an integer vector. The
/// result type must have fewer elements than the operand type, and those
/// elements must be larger integer types such that the total size of the
/// operand type and the result type match. Each of the low operand
/// elements is any-extended into the corresponding, wider result
/// elements with the high bits becoming undef.
ANY_EXTEND_VECTOR_INREG,
/// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
/// in-register sign-extension of the low lanes of an integer vector. The
/// result type must have fewer elements than the operand type, and those
/// elements must be larger integer types such that the total size of the
/// operand type and the result type match. Each of the low operand
/// elements is sign-extended into the corresponding, wider result
/// elements.
// FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
// scalars, but it also doesn't handle vectors well. Either it should be
// restricted to scalars or this node (and its handling) should be merged
// into it.
SIGN_EXTEND_VECTOR_INREG,
/// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
/// in-register zero-extension of the low lanes of an integer vector. The
/// result type must have fewer elements than the operand type, and those

12
include/llvm/CodeGen/SelectionDAG.h
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@ -562,6 +562,18 @@ public:
/// value assuming it was the smaller SrcTy value.
SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);
/// getAnyExtendVectorInReg - Return an operation which will any-extend the
/// low lanes of the operand into the specified vector type. For example,
/// this can convert a v16i8 into a v4i32 by any-extending the low four
/// lanes of the operand from i8 to i32.
SDValue getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
/// getSignExtendVectorInReg - Return an operation which will sign extend the
/// low lanes of the operand into the specified vector type. For example,
/// this can convert a v16i8 into a v4i32 by sign extending the low four
/// lanes of the operand from i8 to i32.
SDValue getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
/// getZeroExtendVectorInReg - Return an operation which will zero extend the
/// low lanes of the operand into the specified vector type. For example,
/// this can convert a v16i8 into a v4i32 by zero extending the low four

2
lib/CodeGen/SelectionDAG/LegalizeTypes.h
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@ -645,11 +645,11 @@ private:
bool WidenVectorOperand(SDNode *N, unsigned OpNo);
SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_STORE(SDNode* N);
SDValue WidenVecOp_SETCC(SDNode* N);
SDValue WidenVecOp_ZERO_EXTEND(SDNode *N);
SDValue WidenVecOp_Convert(SDNode *N);

66
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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@ -75,6 +75,20 @@ class VectorLegalizer {
/// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
SDValue ExpandSEXTINREG(SDValue Op);
/// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
///
/// Shuffles the low lanes of the operand into place and bitcasts to the proper
/// type. The contents of the bits in the extended part of each element are
/// undef.
SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
/// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
///
/// Shuffles the low lanes of the operand into place, bitcasts to the proper
/// type, then shifts left and arithmetic shifts right to introduce a sign
/// extension.
SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
/// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
///
/// Shuffles the low lanes of the operand into place and blends zeros into
@ -280,6 +294,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::FP_EXTEND:
case ISD::FMA:
case ISD::SIGN_EXTEND_INREG:
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
QueryType = Node->getValueType(0);
break;
@ -621,6 +637,10 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
switch (Op->getOpcode()) {
case ISD::SIGN_EXTEND_INREG:
return ExpandSEXTINREG(Op);
case ISD::ANY_EXTEND_VECTOR_INREG:
return ExpandANY_EXTEND_VECTOR_INREG(Op);
case ISD::SIGN_EXTEND_VECTOR_INREG:
return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
case ISD::ZERO_EXTEND_VECTOR_INREG:
return ExpandZERO_EXTEND_VECTOR_INREG(Op);
case ISD::BSWAP:
@ -717,6 +737,52 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
}
// Generically expand a vector anyext in register to a shuffle of the relevant
// lanes into the appropriate locations, with other lanes left undef.
SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
SDLoc DL(Op);
EVT VT = Op.getValueType();
int NumElements = VT.getVectorNumElements();
SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType();
int NumSrcElements = SrcVT.getVectorNumElements();
// Build a base mask of undef shuffles.
SmallVector<int, 16> ShuffleMask;
ShuffleMask.resize(NumSrcElements, -1);
// Place the extended lanes into the correct locations.
int ExtLaneScale = NumSrcElements / NumElements;
int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
for (int i = 0; i < NumElements; ++i)
ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
return DAG.getNode(
ISD::BITCAST, DL, VT,
DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
}
SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType();
// First build an any-extend node which can be legalized above when we
// recurse through it.
Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
// Now we need sign extend. Do this by shifting the elements. Even if these
// aren't legal operations, they have a better chance of being legalized
// without full scalarization than the sign extension does.
unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
return DAG.getNode(ISD::SRA, DL, VT,
DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
ShiftAmount);
}
// Generically expand a vector zext in register to a shuffle of the relevant
// lanes into the appropriate locations, a blend of zero into the high bits,
// and a bitcast to the wider element type.

26
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -2398,7 +2398,12 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
case ISD::STORE: Res = WidenVecOp_STORE(N); break;
case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
case ISD::ZERO_EXTEND: Res = WidenVecOp_ZERO_EXTEND(N); break;
case ISD::ANY_EXTEND:
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
Res = WidenVecOp_EXTEND(N);
break;
case ISD::FP_EXTEND:
case ISD::FP_TO_SINT:
@ -2406,8 +2411,6 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
case ISD::TRUNCATE:
case ISD::SIGN_EXTEND:
case ISD::ANY_EXTEND:
Res = WidenVecOp_Convert(N);
break;
}
@ -2428,14 +2431,14 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
return false;
}
SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue InOp = N->getOperand(0);
// If some legalization strategy other than widening is used on the operand,
// we can't safely assume that just zero-extending the low lanes is the
// correct transformation.
// we can't safely assume that just extending the low lanes is the correct
// transformation.
if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
return WidenVecOp_Convert(N);
InOp = GetWidenedVector(InOp);
@ -2476,10 +2479,19 @@ SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
return WidenVecOp_Convert(N);
}
// Use a special DAG node to represent the operation of zero extending the
// Use special DAG nodes to represent the operation of extending the
// low lanes.
switch (N->getOpcode()) {
default:
llvm_unreachable("Extend legalization on on extend operation!");
case ISD::ANY_EXTEND:
return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
case ISD::SIGN_EXTEND:
return DAG.getSignExtendVectorInReg(InOp, DL, VT);
case ISD::ZERO_EXTEND:
return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
}
}
SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
// Since the result is legal and the input is illegal, it is unlikely

20
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1033,6 +1033,26 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) {
getConstant(Imm, Op.getValueType()));
}
SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
assert(VT.isVector() && "This DAG node is restricted to vector types.");
assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&
"The sizes of the input and result must match in order to perform the "
"extend in-register.");
assert(VT.getVectorNumElements() < Op.getValueType().getVectorNumElements() &&
"The destination vector type must have fewer lanes than the input.");
return getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Op);
}
SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
assert(VT.isVector() && "This DAG node is restricted to vector types.");
assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&
"The sizes of the input and result must match in order to perform the "
"extend in-register.");
assert(VT.getVectorNumElements() < Op.getValueType().getVectorNumElements() &&
"The destination vector type must have fewer lanes than the input.");
return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op);
}
SDValue SelectionDAG::getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
assert(VT.isVector() && "This DAG node is restricted to vector types.");
assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&

2
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
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@ -221,6 +221,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::ZERO_EXTEND: return "zero_extend";
case ISD::ANY_EXTEND: return "any_extend";
case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
case ISD::TRUNCATE: return "truncate";
case ISD::FP_ROUND: return "fp_round";

4
lib/CodeGen/TargetLoweringBase.cpp
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@ -746,6 +746,10 @@ void TargetLoweringBase::initActions() {
if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
VT <= MVT::LAST_VECTOR_VALUETYPE) {
setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,
(MVT::SimpleValueType)VT, Expand);
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG,
(MVT::SimpleValueType)VT, Expand);
setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG,
(MVT::SimpleValueType)VT, Expand);
}

18
test/CodeGen/X86/vec_cast2.ll
View File

@ -4,6 +4,17 @@
;CHECK-LABEL: foo1_8:
;CHECK: vcvtdq2ps
;CHECK: ret
;
;CHECK-WIDE-LABEL: foo1_8:
;CHECK-WIDE: vpmovzxbd %xmm0, %xmm1
;CHECK-WIDE-NEXT: vpslld $24, %xmm1, %xmm1
;CHECK-WIDE-NEXT: vpsrad $24, %xmm1, %xmm1
;CHECK-WIDE-NEXT: vpshufb {{.*}}, %xmm0, %xmm0
;CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
;CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
;CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
;CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0
;CHECK-WIDE-NEXT: ret
define <8 x float> @foo1_8(<8 x i8> %src) {
%res = sitofp <8 x i8> %src to <8 x float>
ret <8 x float> %res
@ -12,6 +23,13 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
;CHECK-LABEL: foo1_4:
;CHECK: vcvtdq2ps
;CHECK: ret
;
;CHECK-WIDE-LABEL: foo1_4:
;CHECK-WIDE: vpmovzxbd %xmm0, %xmm0
;CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
;CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
;CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
;CHECK-WIDE-NEXT: ret
define <4 x float> @foo1_4(<4 x i8> %src) {
%res = sitofp <4 x i8> %src to <4 x float>
ret <4 x float> %res