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[mips][microMIPS] MicroMIPS Compact Branch Instructions BEQZC and BNEZC

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Differential Revision: http://reviews.llvm.org/D3545


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215636 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-08-14 12:09:10 +00:00
parent 43d6849e95
commit cdcacd7568
2 changed files with 28 additions and 0 deletions
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12
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -621,3 +621,15 @@ class MADDS_FM_MM<bits<6> funct>: MMArch {
let Inst{10-6} = fr;
let Inst{5-0} = funct;
}
class COMPACT_BRANCH_FM_MM<bits<5> funct> {
bits<5> rs;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 0x10;
let Inst{25-21} = funct;
let Inst{20-16} = rs;
let Inst{15-0} = offset;
}

16
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -26,6 +26,16 @@ def brtarget_mm : Operand<OtherVT> {
let DecoderMethod = "DecodeBranchTargetMM";
}
class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
!strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 0;
let Defs = [AT];
}
let canFoldAsLoad = 1 in
class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
Operand MemOpnd> :
@ -104,6 +114,12 @@ class WaitMM<string opstr> :
NoItinerary, FrmOther, opstr>;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Compact Branch Instructions
def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
COMPACT_BRANCH_FM_MM<0x7>;
def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
COMPACT_BRANCH_FM_MM<0x5>;
/// Arithmetic Instructions (ALU Immediate)
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
ADDI_FM_MM<0xc>;