6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

AArch64: Fix a bug about disassembling post-index load single element to 4 vectors

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu 2013-11-28 01:07:45 +00:00
parent 18a777a09a
commit cdd732cdd3
2 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
View File

@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
switch (Opc) {
case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
TransferBytes = 3; break;
TransferBytes = 4; break;
case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
TransferBytes = 6; break;
TransferBytes = 8; break;
case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
TransferBytes = 12; break;
TransferBytes = 16; break;
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
TransferBytes = 24; break;
TransferBytes = 32; break;
}
IsLoad = true;
NumVecs = 4;

4
test/MC/Disassembler/AArch64/neon-instructions.txt
View File

@ -2129,7 +2129,8 @@
# CHECK: ld1 {v0.b}[9], [x0], #1
# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
# CHECK: st1 {v0.d}[1], [x0], #8
# CHECK: st2 {v31.s, v0.s}[3], [sp], #8
# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
@ -2138,6 +2139,7 @@
0xef,0x59,0xff,0x4d
0xff,0xb3,0xc3,0x4d
0x00,0xa4,0xff,0x4d
0x00,0x78,0xe0,0x4d
0x00,0x84,0x9f,0x4d
0xff,0x93,0xbf,0x4d
0xef,0x79,0x9f,0x4d