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Code Issues Projects Releases Wiki Activity

* Doxygenify comments

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* Fix spacing, grammar in comment
* Make code layout consistent
* Wrap code at 80 cols
* Delete spurious blank lines

No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-09 14:45:17 +00:00
parent 80b27ced2d
commit ce22e76996
1 changed files with 95 additions and 103 deletions
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40
lib/CodeGen/MachineInstr.cpp
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@ -72,6 +72,7 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
}
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
Opcode = MI.getOpcode();
numImplicitRefs = MI.getNumImplicitRefs();
@ -85,18 +86,16 @@ MachineInstr::MachineInstr(const MachineInstr &MI) {
parent = 0;
prev = 0;
next = 0;
}
MachineInstr::~MachineInstr()
{
MachineInstr::~MachineInstr() {
LeakDetector::removeGarbageObject(this);
}
///clone - Create a copy of 'this' instruction that is identical in
///all ways except the following: The instruction has no parent The
///instruction has no name
/// clone - Create a copy of 'this' instruction that is identical in all ways
/// except the following: the new instruction has no parent and it has no name
///
MachineInstr* MachineInstr::clone() const {
return new MachineInstr(*this);
}
@ -120,7 +119,6 @@ void MachineInstr::replace(short opcode, unsigned numOperands) {
Opcode = opcode;
operands.clear();
operands.resize(numOperands, MachineOperand());
}
void MachineInstr::SetMachineOperandVal(unsigned i,
@ -192,23 +190,22 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
{
O.getMachineOperand().contents.value = newVal;
++numSubst;
}
else
} else
someArgsWereIgnored = true;
// Substitute implicit refs
for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
if (getImplicitRef(i) == oldVal) {
MachineOperand Op = getImplicitOp(i);
if (!defsOnly ||
notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
!notDefsAndUses && getImplicitOp(i).isDef())
notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
!notDefsAndUses && Op.isDef())
{
getImplicitOp(i).contents.value = newVal;
Op.contents.value = newVal;
++numSubst;
}
else
} else
someArgsWereIgnored = true;
}
return numSubst;
}
@ -238,12 +235,9 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine *TM) {
const MRegisterInfo *MRI = 0;
if(TM)
MRI = TM->getRegisterInfo();
if (TM) MRI = TM->getRegisterInfo();
bool CloseParen = true;
if (MO.isHiBits32())
@ -421,8 +415,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
else if (MO.isLoBits64())
OS << "%hm(";
switch (MO.getType())
{
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getReg());
@ -450,8 +443,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
case MachineOperand::MO_UnextendedImmed:
OS << (long)MO.getImmedValue();
break;
case MachineOperand::MO_PCRelativeDisp:
{
case MachineOperand::MO_PCRelativeDisp: {
const Value* opVal = MO.getVRegValue();
bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
OS << "%disp(" << (isLabel? "label " : "addr-of-val ");