mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
Cleanup Mips code and rename some variables. Patch by Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
3aa035fa0c
commit
ce8524c016
@ -66,10 +66,10 @@ static bool isDirective(unsigned Opc) {
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}
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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if (MI->isDebugValue()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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PrintDebugValueComment(MI, OS);
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return;
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}
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@ -178,7 +178,7 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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if (Mips::CPURegsRegisterClass->contains(Reg))
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break;
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
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unsigned RegNum = getMipsRegisterNumbering(Reg);
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if (Mips::AFGR64RegisterClass->contains(Reg)) {
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FPUBitmask |= (3 << RegNum);
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CSFPRegsSize += AFGR64RegSize;
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@ -193,7 +193,7 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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// Set CPU Bitmask.
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for (; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
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unsigned RegNum = getMipsRegisterNumbering(Reg);
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CPUBitmask |= (1 << RegNum);
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}
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@ -216,7 +216,7 @@ unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI,
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unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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if (MO.isReg())
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return MipsRegisterInfo::getRegisterNumbering(MO.getReg());
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return getMipsRegisterNumbering(MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobal()) {
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@ -213,102 +213,102 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst,
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4>& MCInsts) {
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unsigned Opc = MI->getOpcode();
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MCInst instr1, instr2, instr3, move;
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MCInst Instr1, Instr2, Instr3, Move;
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bool two_instructions = false;
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bool TwoInstructions = false;
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assert(MI->getNumOperands() == 3);
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assert(MI->getOperand(0).isReg());
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assert(MI->getOperand(1).isReg());
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MCOperand target = LowerOperand(MI->getOperand(0));
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MCOperand base = LowerOperand(MI->getOperand(1));
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MCOperand atReg = MCOperand::CreateReg(Mips::AT);
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MCOperand zeroReg = MCOperand::CreateReg(Mips::ZERO);
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MCOperand Target = LowerOperand(MI->getOperand(0));
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MCOperand Base = LowerOperand(MI->getOperand(1));
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MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
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MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
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MachineOperand unloweredName = MI->getOperand(2);
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MCOperand name = LowerOperand(unloweredName);
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MachineOperand UnLoweredName = MI->getOperand(2);
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MCOperand Name = LowerOperand(UnLoweredName);
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move.setOpcode(Mips::ADDu);
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move.addOperand(target);
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move.addOperand(atReg);
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move.addOperand(zeroReg);
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Move.setOpcode(Mips::ADDu);
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Move.addOperand(Target);
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Move.addOperand(ATReg);
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Move.addOperand(ZeroReg);
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switch (Opc) {
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case Mips::ULW: {
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// FIXME: only works for little endian right now
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MCOperand adj_name = LowerOperand(unloweredName, 3);
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if (base.getReg() == (target.getReg())) {
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instr1.setOpcode(Mips::LWL);
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instr1.addOperand(atReg);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LWR);
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instr2.addOperand(atReg);
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instr2.addOperand(base);
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instr2.addOperand(name);
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instr3 = move;
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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if (Base.getReg() == (Target.getReg())) {
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3 = Move;
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} else {
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two_instructions = true;
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instr1.setOpcode(Mips::LWL);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LWR);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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TwoInstructions = true;
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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}
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break;
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}
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case Mips::ULHu: {
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// FIXME: only works for little endian right now
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MCOperand adj_name = LowerOperand(unloweredName, 1);
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instr1.setOpcode(Mips::LBu);
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instr1.addOperand(atReg);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::LBu);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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instr3.setOpcode(Mips::INS);
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instr3.addOperand(target);
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instr3.addOperand(atReg);
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instr3.addOperand(MCOperand::CreateImm(0x8));
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instr3.addOperand(MCOperand::CreateImm(0x18));
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::LBu);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LBu);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3.setOpcode(Mips::INS);
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Instr3.addOperand(Target);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(MCOperand::CreateImm(0x8));
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Instr3.addOperand(MCOperand::CreateImm(0x18));
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break;
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}
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case Mips::USW: {
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// FIXME: only works for little endian right now
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assert (base.getReg() != target.getReg());
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two_instructions = true;
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MCOperand adj_name = LowerOperand(unloweredName, 3);
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instr1.setOpcode(Mips::SWL);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(adj_name);
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instr2.setOpcode(Mips::SWR);
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instr2.addOperand(target);
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instr2.addOperand(base);
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instr2.addOperand(name);
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assert (Base.getReg() != Target.getReg());
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TwoInstructions = true;
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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Instr1.setOpcode(Mips::SWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::SWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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break;
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}
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case Mips::USH: {
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MCOperand adj_name = LowerOperand(unloweredName, 1);
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instr1.setOpcode(Mips::SB);
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instr1.addOperand(target);
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instr1.addOperand(base);
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instr1.addOperand(name);
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instr2.setOpcode(Mips::SRL);
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instr2.addOperand(atReg);
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instr2.addOperand(target);
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instr2.addOperand(MCOperand::CreateImm(8));
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instr3.setOpcode(Mips::SB);
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instr3.addOperand(atReg);
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instr3.addOperand(base);
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instr3.addOperand(adj_name);
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::SB);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(Name);
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Instr2.setOpcode(Mips::SRL);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Target);
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Instr2.addOperand(MCOperand::CreateImm(8));
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Instr3.setOpcode(Mips::SB);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(Base);
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Instr3.addOperand(AdjName);
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break;
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}
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default:
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@ -316,8 +316,8 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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assert(0 && "unaligned instruction not processed");
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}
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MCInsts.push_back(instr1);
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MCInsts.push_back(instr2);
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if (!two_instructions) MCInsts.push_back(instr3);
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MCInsts.push_back(Instr1);
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MCInsts.push_back(Instr2);
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if (!TwoInstructions) MCInsts.push_back(Instr3);
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}
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@ -45,98 +45,6 @@ MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
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const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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unsigned MipsRegisterInfo::
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getRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
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case Mips::D0:
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return 0;
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case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
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return 1;
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case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
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case Mips::D1:
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return 2;
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case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
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return 3;
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case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
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case Mips::D2:
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return 4;
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case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
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return 5;
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case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
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case Mips::D3:
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return 6;
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case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
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return 7;
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case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
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case Mips::D4:
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return 8;
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case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
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return 9;
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case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
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case Mips::D5:
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return 10;
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case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
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return 11;
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case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
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case Mips::D6:
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return 12;
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case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
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return 13;
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case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
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case Mips::D7:
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return 14;
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case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
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return 15;
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case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
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case Mips::D8:
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return 16;
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case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
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return 17;
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case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
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case Mips::D9:
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return 18;
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case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
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return 19;
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case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
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case Mips::D10:
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return 20;
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case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
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return 21;
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case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
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case Mips::D11:
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return 22;
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case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
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return 23;
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case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
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case Mips::D12:
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return 24;
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case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
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return 25;
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case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
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case Mips::D13:
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return 26;
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case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
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return 27;
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case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
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case Mips::D14:
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return 28;
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case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
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case Mips::HWR29:
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return 29;
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case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
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case Mips::D15:
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return 30;
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case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
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return 31;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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}
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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//===----------------------------------------------------------------------===//
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