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Split ExtIns into two base classes and have instructions EXT and INS derive from
them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -623,14 +623,29 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
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}
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// Ext and Ins
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class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
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list<dag> pattern, InstrItinClass itin>:
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FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
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pattern, itin>, Requires<[HasMips32r2]> {
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class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
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FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
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!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
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[(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
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bits<5> pos;
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bits<5> sz;
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let rd = sz;
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let shamt = pos;
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let Predicates = [HasMips32r2];
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}
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class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
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FR<0x1f, _funct, (outs RC:$rt),
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(ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
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!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
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[(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
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NoItinerary> {
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bits<5> pos;
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bits<5> sz;
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let rd = sz;
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let shamt = pos;
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let Predicates = [HasMips32r2];
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let Constraints = "$src = $rt";
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}
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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@ -890,19 +905,8 @@ def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
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def RDHWR : ReadHardware;
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def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
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(ins CPURegs:$rs, uimm16:$pos, size_ext:$sz),
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[(set CPURegs:$rt,
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(MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
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NoItinerary>;
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let Constraints = "$src = $rt" in
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def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
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(ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src),
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[(set CPURegs:$rt,
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(MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
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CPURegs:$src))],
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NoItinerary>;
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def EXT : ExtBase<0, "ext", CPURegs>;
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def INS : InsBase<4, "ins", CPURegs>;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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