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Fixing a bunch of -Woverloaded-virtual warnings due to hiding getSubtargetImpl from the base class. NFC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman 2014-09-18 13:27:14 +00:00
parent 6c0e053dc9
commit cf5bea8e4a
12 changed files with 14 additions and 0 deletions
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1
lib/Target/AArch64/AArch64TargetMachine.h
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@ -31,6 +31,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool IsLittleEndian);
using LLVMTargetMachine::getSubtargetImpl;
const AArch64Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}

1
lib/Target/ARM/ARMTargetMachine.h
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@ -32,6 +32,7 @@ public:
CodeGenOpt::Level OL,
bool isLittle);
using LLVMTargetMachine::getSubtargetImpl;
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register ARM analysis passes with a pass manager.

1
lib/Target/Hexagon/HexagonTargetMachine.h
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@ -31,6 +31,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const HexagonSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

1
lib/Target/MSP430/MSP430TargetMachine.h
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@ -32,6 +32,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const MSP430Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}

1
lib/Target/Mips/MipsTargetMachine.h
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@ -39,6 +39,7 @@ public:
void addAnalysisPasses(PassManagerBase &PM) override;
using LLVMTargetMachine::getSubtargetImpl;
const MipsSubtarget *getSubtargetImpl() const override {
if (Subtarget)
return Subtarget;

1
lib/Target/NVPTX/NVPTXTargetMachine.h
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@ -35,6 +35,7 @@ public:
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
using LLVMTargetMachine::getSubtargetImpl;
const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
ManagedStringPool *getManagedStrPool() const {

1
lib/Target/PowerPC/PPCTargetMachine.h
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@ -32,6 +32,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration

2
lib/Target/R600/AMDGPUTargetMachine.h
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@ -33,6 +33,8 @@ public:
StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine();
using LLVMTargetMachine::getSubtargetImpl;
const AMDGPUSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

1
lib/Target/Sparc/SparcTargetMachine.h
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@ -28,6 +28,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit);
using LLVMTargetMachine::getSubtargetImpl;
const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration

1
lib/Target/SystemZ/SystemZTargetMachine.h
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@ -32,6 +32,7 @@ public:
CodeGenOpt::Level OL);
// Override TargetMachine.
using LLVMTargetMachine::getSubtargetImpl;
const SystemZSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

2
lib/Target/X86/X86TargetMachine.h
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@ -31,6 +31,8 @@ public:
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register X86 analysis passes with a pass manager.

1
lib/Target/XCore/XCoreTargetMachine.h
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@ -27,6 +27,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration