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misched: Don't consider artificial edges weak edges.

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For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-11-13 02:35:06 +00:00
parent e7ff4c14b1
commit cf6b6131dd
3 changed files with 6 additions and 11 deletions
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3
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -206,8 +206,7 @@ namespace llvm {
/// not force ordering. Breaking a weak edge may require the scheduler to
/// compensate, for example by inserting a copy.
bool isWeak() const {
return getKind() == Order
&& (Contents.OrdKind == Artificial || Contents.OrdKind == Cluster);
return getKind() == Order && Contents.OrdKind == Cluster;
}
/// isArtificial - Test if this is an Order dependence that is marked

2
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -581,7 +581,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
SUnit *SuccSU = SuccEdge->getSUnit();
if (SuccEdge->isArtificial()) {
if (SuccEdge->isWeak()) {
--SuccSU->WeakPredsLeft;
return;
}

12
lib/CodeGen/ScheduleDAG.cpp
View File

@ -100,11 +100,8 @@ bool SUnit::addPred(const SDep &D, bool Required) {
++NumPreds;
++N->NumSuccs;
}
// SD scheduler relies on artificial edges to enforce physreg
// antidependence, so it doesn't treat them as weak edges.
bool isWeak = D.isWeak() && N->isInstr();
if (!N->isScheduled) {
if (isWeak) {
if (D.isWeak()) {
++WeakPredsLeft;
}
else {
@ -113,7 +110,7 @@ bool SUnit::addPred(const SDep &D, bool Required) {
}
}
if (!isScheduled) {
if (isWeak) {
if (D.isWeak()) {
++N->WeakSuccsLeft;
}
else {
@ -160,9 +157,8 @@ void SUnit::removePred(const SDep &D) {
--NumPreds;
--N->NumSuccs;
}
bool isWeak = D.isWeak() && N->isInstr();
if (!N->isScheduled) {
if (isWeak)
if (D.isWeak())
--WeakPredsLeft;
else {
assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
@ -170,7 +166,7 @@ void SUnit::removePred(const SDep &D) {
}
}
if (!isScheduled) {
if (isWeak)
if (D.isWeak())
--N->WeakSuccsLeft;
else {
assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");