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[Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239744 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,50 +15,6 @@
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGON_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGON_H
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class HexagonAsmPrinter;
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class HexagonTargetMachine;
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class MachineInstr;
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class MCInst;
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class ModulePass;
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class raw_ostream;
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class TargetMachine;
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonDelaySlotFillerPass(const TargetMachine &TM);
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FunctionPass *createHexagonFPMoverPass(const TargetMachine &TM);
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FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonExpandPredSpillCode();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonPacketizer();
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FunctionPass *createHexagonNewValueJump();
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/* TODO: object output.
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MCCodeEmitter *createHexagonMCCodeEmitter(const Target &,
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const TargetMachine &TM,
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MCContext &Ctx);
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*/
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/* TODO: assembler input.
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TargetAsmBackend *createHexagonAsmBackend(const Target &,
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const std::string &);
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*/
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void HexagonLowerToMC(MachineInstr const *MI, MCInst &MCI,
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HexagonAsmPrinter &AP);
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} // end namespace llvm;
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#define Hexagon_POINTER_SIZE 4
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#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
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@ -75,7 +31,7 @@ namespace llvm {
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// Maximum number of words and instructions in a packet.
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#define HEXAGON_PACKET_SIZE 4
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#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
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// Minimum number of instructions in an end-loop packet.
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#define HEXAGON_PACKET_INNER_SIZE 2
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#define HEXAGON_PACKET_OUTER_SIZE 3
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@ -83,4 +39,25 @@ namespace llvm {
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// including a compound one or a duplex or an extender.
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#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
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// Name of the global offset table as defined by the Hexagon ABI
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#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class MachineInstr;
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class MCInst;
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class MCInstrInfo;
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class HexagonAsmPrinter;
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class HexagonTargetMachine;
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void HexagonLowerToMC(const MachineInstr *MI, MCInst &MCI,
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HexagonAsmPrinter &AP);
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/// \brief Creates a Hexagon-specific Target Transformation Info pass.
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ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
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} // end namespace llvm;
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#endif
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@ -28,6 +28,7 @@ using namespace llvm;
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#define DEBUG_TYPE "hexagon_cfg"
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namespace llvm {
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FunctionPass *createHexagonCFGOptimizer();
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void initializeHexagonCFGOptimizerPass(PassRegistry&);
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}
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@ -49,6 +49,7 @@ MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
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"consider the store still to be newifiable"));
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namespace llvm {
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FunctionPass *createHexagonCopyToCombine();
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void initializeHexagonCopyToCombinePass(PassRegistry&);
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}
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@ -41,6 +41,7 @@ using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonExpandPredSpillCode();
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void initializeHexagonExpandPredSpillCodePass(PassRegistry&);
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}
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@ -30,6 +30,7 @@ static cl::opt<unsigned> MaxLoopRange(
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cl::desc("Restrict range of loopN instructions (testing only)"));
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namespace llvm {
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FunctionPass *createHexagonFixupHwLoops();
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void initializeHexagonFixupHwLoopsPass(PassRegistry&);
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}
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@ -63,6 +63,7 @@ static cl::opt<bool> HWCreatePreheader("hexagon-hwloop-preheader",
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STATISTIC(NumHWLoops, "Number of loops converted to hardware loops");
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namespace llvm {
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FunctionPass *createHexagonHardwareLoops();
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void initializeHexagonHardwareLoopsPass(PassRegistry&);
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}
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@ -60,6 +60,7 @@ static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
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cl::desc("Disable New Value Jumps"));
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namespace llvm {
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FunctionPass *createHexagonNewValueJump();
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void initializeHexagonNewValueJumpPass(PassRegistry&);
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}
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@ -75,6 +75,7 @@ static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
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cl::desc("Disable Optimization of extensions to i64."));
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namespace llvm {
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FunctionPass *createHexagonPeephole();
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void initializeHexagonPeepholePass(PassRegistry&);
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}
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@ -24,6 +24,7 @@
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using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
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void initializeHexagonRemoveExtendArgsPass(PassRegistry&);
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}
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@ -45,6 +45,11 @@ using namespace llvm;
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#define DEBUG_TYPE "xfer"
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namespace llvm {
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FunctionPass *createHexagonSplitConst32AndConst64();
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void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&);
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}
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namespace {
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class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
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@ -61,7 +61,23 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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namespace llvm {
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FunctionPass *createHexagonExpandCondsets();
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}
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonDelaySlotFillerPass(const TargetMachine &TM);
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FunctionPass *createHexagonFPMoverPass(const TargetMachine &TM);
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FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonExpandPredSpillCode();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonPacketizer();
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FunctionPass *createHexagonNewValueJump();
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} // end namespace llvm;
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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cl::desc("Allow non-solo packetization of volatile memory references"));
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namespace llvm {
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FunctionPass *createHexagonPacketizer();
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void initializeHexagonPacketizerPass(PassRegistry&);
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}
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uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB,
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MCInst const &MCI) const;
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MCSubtargetInfo const &getSubtargetInfo() const;
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void encodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const override;
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@ -65,10 +63,6 @@ public:
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unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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private:
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HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete;
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void operator=(HexagonMCCodeEmitter const &) = delete;
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}; // class HexagonMCCodeEmitter
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} // namespace llvm
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