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Remove the xaddroff ComplexPattern.

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The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns.  This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-03-22 14:57:48 +00:00
parent c446baa0be
commit cff0faa16a
3 changed files with 18 additions and 31 deletions
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12
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -132,18 +132,6 @@ namespace {
return false; return false;
} }
/// SelectAddrIdxOffs - Return true if the operand is valid for a preinc
/// index field. Because preinc imms have already been validated, just
/// accept it.
bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const {
if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
N.getOpcode() == ISD::TargetGlobalAddress)
return false;
Out = N;
return true;
}
/// SelectAddrIdx - Given the specified addressed, check to see if it can be /// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can /// represented as an indexed [r+r] operation. Returns false if it can
/// be represented by [r+imm], which are preferred. /// be represented by [r+imm], which are preferred.

16
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -875,14 +875,14 @@ def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
(STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; (STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STBUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STBUX8 G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STHUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STHUX8 G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STWUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STWUX8 G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_store G8RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STDUX G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STDUX G8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

21
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -424,7 +424,6 @@ def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
/// This is just the offset part of iaddr, used for preinc. /// This is just the offset part of iaddr, used for preinc.
def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions. // PowerPC Instruction Predicate Definitions.
@ -1005,16 +1004,16 @@ def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$d
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STBUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STBUX GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STHUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STHUX GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STWUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STWUX GPRC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_store F4RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STFSUX F4RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STFSUX F4RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def : Pat<(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), def : Pat<(pre_store F8RC:$rS, ptr_rc:$ptrreg, ptr_rc_nor0:$ptroff),
(STFDUX F8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; (STFDUX F8RC:$rS, ptr_rc_nor0:$ptroff, ptr_rc:$ptrreg)>;
def SYNC : XForm_24_sync<31, 598, (outs), (ins), def SYNC : XForm_24_sync<31, 598, (outs), (ins),
"sync", LdStSync, "sync", LdStSync,