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AVX-512: Added patterns for scalar-to-vector broadcast

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237558 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-05-18 07:06:23 +00:00
parent c4a426be4f
commit d026e5020b
2 changed files with 38 additions and 0 deletions
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10
lib/Target/X86/X86InstrAVX512.td
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@ -941,13 +941,23 @@ def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
(VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
(VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
(VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
(VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
(VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
(VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
(VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
(VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
(VBROADCASTSSZr VR128X:$src)>;

28
test/CodeGen/X86/avx512-vbroadcast.ll
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@ -300,3 +300,31 @@ entry:
%vecinit7.i = insertelement <8 x double> %vecinit6.i, double %0, i32 7
ret <8 x double> %vecinit7.i
}
; CHECK-LABEL: test1
; CHECK: vbroadcastss
define <16 x float> @test1(<8 x float>%a) {
%res = shufflevector <8 x float> %a, <8 x float> undef, <16 x i32> zeroinitializer
ret <16 x float>%res
}
; CHECK-LABEL: test2
; CHECK: vbroadcastsd
define <8 x double> @test2(<4 x double>%a) {
%res = shufflevector <4 x double> %a, <4 x double> undef, <8 x i32> zeroinitializer
ret <8 x double>%res
}
; CHECK-LABEL: test3
; CHECK: vpbroadcastd
define <16 x i32> @test3(<8 x i32>%a) {
%res = shufflevector <8 x i32> %a, <8 x i32> undef, <16 x i32> zeroinitializer
ret <16 x i32>%res
}
; CHECK-LABEL: test4
; CHECK: vpbroadcastq
define <8 x i64> @test4(<4 x i64>%a) {
%res = shufflevector <4 x i64> %a, <4 x i64> undef, <8 x i32> zeroinitializer
ret <8 x i64>%res
}