6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 22:24:07 +00:00
Code Issues Projects Releases Wiki Activity

Fix for PR14824, An ARM Load/Store Optimization bug

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
2013-04-18 09:11:08 +00:00
parent 7754276c4c
commit d050e96133
2 changed files with 99 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -1258,6 +1258,22 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// merge the ldr's so far, including this one. But don't try to
// combine the following ldr(s).
Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
// Watch out for:
// r4 := ldr [r0, #8]
// r4 := ldr [r0, #4]
//
// The optimization may reorder the second ldr in front of the first
// ldr, which violates write after write(WAW) dependence. The same as
// str. Try to merge inst(s) already in MemOps.
bool Overlap = false;
for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end(); I != E; ++I) {
if (TRI->regsOverlap(Reg, I->MBBI->getOperand(0).getReg())) {
Overlap = true;
break;
}
}
if (CurrBase == 0 && !Clobber) {
// Start of a new chain.
CurrBase = Base;
@ -1268,7 +1284,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
++NumMemOps;
Advance = true;
} else {
} else if (!Overlap) {
if (Clobber) {
TryMerge = true;
Advance = true;