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Intel mode no longer uses %'s on registers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-05-01 05:56:51 +00:00
parent 99f2632b4b
commit d065c813c8
6 changed files with 7 additions and 7 deletions
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2
test/CodeGen/X86/fast-cc-pass-in-regs.ll
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@@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov %EDX, 1'
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov EDX, 1'
; check that fastcc is passing stuff in regs.
; Argument reg passing is disabled due to regalloc issues. FIXME!