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[FastISel][X86] Add support for floating-point select.
This extends the select lowering to support floating-point selects. The lowering depends on SSE instructions and that the conditon comes from a floating-point compare. Under this conditions it is possible to emit an optimized instruction sequence that doesn't require any branches to simulate the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211544 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
5f4e6e1ec0
commit
d0976a3d20
@ -113,6 +113,8 @@ private:
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bool X86FastEmitCMoveSelect(const Instruction *I);
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bool X86FastEmitSSESelect(const Instruction *I);
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bool X86SelectSelect(const Instruction *I);
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bool X86SelectTrunc(const Instruction *I);
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@ -235,6 +237,41 @@ getX86ConditonCode(CmpInst::Predicate Predicate) {
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return std::make_pair(CC, NeedSwap);
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}
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static std::pair<unsigned, bool>
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getX86SSECondtionCode(CmpInst::Predicate Predicate) {
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unsigned CC;
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bool NeedSwap = false;
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// SSE Condition code mapping:
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// 0 - EQ
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// 1 - LT
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// 2 - LE
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// 3 - UNORD
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// 4 - NEQ
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// 5 - NLT
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// 6 - NLE
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// 7 - ORD
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switch (Predicate) {
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default: llvm_unreachable("Unexpected predicate");
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case CmpInst::FCMP_OEQ: CC = 0; break;
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case CmpInst::FCMP_OGT: NeedSwap = true; // fall-through
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case CmpInst::FCMP_OLT: CC = 1; break;
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case CmpInst::FCMP_OGE: NeedSwap = true; // fall-through
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case CmpInst::FCMP_OLE: CC = 2; break;
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case CmpInst::FCMP_UNO: CC = 3; break;
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case CmpInst::FCMP_UNE: CC = 4; break;
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case CmpInst::FCMP_ULE: NeedSwap = true; // fall-through
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case CmpInst::FCMP_UGE: CC = 5; break;
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case CmpInst::FCMP_ULT: NeedSwap = true; // fall-through
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case CmpInst::FCMP_UGT: CC = 6; break;
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case CmpInst::FCMP_ORD: CC = 7; break;
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case CmpInst::FCMP_UEQ:
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case CmpInst::FCMP_ONE: CC = 8; break;
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}
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return std::make_pair(CC, NeedSwap);
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}
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bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
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EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
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if (evt == MVT::Other || !evt.isSimple())
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@ -1728,6 +1765,93 @@ bool X86FastISel::X86FastEmitCMoveSelect(const Instruction *I) {
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return true;
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}
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/// \brief Emit SSE instructions to lower the select.
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///
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/// Try to use SSE1/SSE2 instructions to simulate a select without branches.
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/// This lowers fp selects into a CMP/AND/ANDN/OR sequence when the necessary
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/// SSE instructions are available.
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bool X86FastISel::X86FastEmitSSESelect(const Instruction *I) {
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MVT RetVT;
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if (!isTypeLegal(I->getType(), RetVT))
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return false;
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const auto *CI = dyn_cast<FCmpInst>(I->getOperand(0));
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if (!CI)
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return false;
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if (I->getType() != CI->getOperand(0)->getType() ||
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!((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
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(Subtarget->hasSSE2() && RetVT == MVT::f64) ))
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return false;
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const Value *CmpLHS = CI->getOperand(0);
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const Value *CmpRHS = CI->getOperand(1);
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CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
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// The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0.
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// We don't have to materialize a zero constant for this case and can just use
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// %x again on the RHS.
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if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
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const auto *CmpRHSC = dyn_cast<ConstantFP>(CmpRHS);
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if (CmpRHSC && CmpRHSC->isNullValue())
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CmpRHS = CmpLHS;
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}
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unsigned CC;
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bool NeedSwap;
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std::tie(CC, NeedSwap) = getX86SSECondtionCode(Predicate);
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if (CC > 7)
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return false;
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if (NeedSwap)
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std::swap(CmpLHS, CmpRHS);
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static unsigned OpcTable[2][2][4] = {
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{ { X86::CMPSSrr, X86::FsANDPSrr, X86::FsANDNPSrr, X86::FsORPSrr },
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{ X86::VCMPSSrr, X86::VFsANDPSrr, X86::VFsANDNPSrr, X86::VFsORPSrr } },
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{ { X86::CMPSDrr, X86::FsANDPDrr, X86::FsANDNPDrr, X86::FsORPDrr },
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{ X86::VCMPSDrr, X86::VFsANDPDrr, X86::VFsANDNPDrr, X86::VFsORPDrr } }
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};
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bool HasAVX = Subtarget->hasAVX();
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unsigned *Opc = nullptr;
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switch (RetVT.SimpleTy) {
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default: return false;
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case MVT::f32: Opc = &OpcTable[0][HasAVX][0]; break;
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case MVT::f64: Opc = &OpcTable[1][HasAVX][0]; break;
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}
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const Value *LHS = I->getOperand(1);
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const Value *RHS = I->getOperand(2);
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unsigned LHSReg = getRegForValue(LHS);
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bool LHSIsKill = hasTrivialKill(LHS);
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unsigned RHSReg = getRegForValue(RHS);
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bool RHSIsKill = hasTrivialKill(RHS);
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unsigned CmpLHSReg = getRegForValue(CmpLHS);
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bool CmpLHSIsKill = hasTrivialKill(CmpLHS);
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unsigned CmpRHSReg = getRegForValue(CmpRHS);
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bool CmpRHSIsKill = hasTrivialKill(CmpRHS);
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if (!LHSReg || !RHSReg || !CmpLHS || !CmpRHS)
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return false;
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const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
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unsigned CmpReg = FastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill,
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CmpRHSReg, CmpRHSIsKill, CC);
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unsigned AndReg = FastEmitInst_rr(Opc[1], RC, CmpReg, /*IsKill=*/false,
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LHSReg, LHSIsKill);
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unsigned AndNReg = FastEmitInst_rr(Opc[2], RC, CmpReg, /*IsKill=*/true,
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RHSReg, RHSIsKill);
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unsigned ResultReg = FastEmitInst_rr(Opc[3], RC, AndNReg, /*IsKill=*/true,
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AndReg, /*IsKill=*/true);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool X86FastISel::X86SelectSelect(const Instruction *I) {
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MVT RetVT;
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if (!isTypeLegal(I->getType(), RetVT))
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@ -1762,6 +1886,10 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) {
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if (X86FastEmitCMoveSelect(I))
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return true;
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// Try to use a sequence of SSE instructions to simulate a conditonal move.
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if (X86FastEmitSSESelect(I))
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return true;
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return false;
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}
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391
test/CodeGen/X86/fast-isel-select-sse.ll
Normal file
391
test/CodeGen/X86/fast-isel-select-sse.ll
Normal file
@ -0,0 +1,391 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
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; Test all cmp predicates that can be used with SSE.
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define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_oeq_f32
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; CHECK: cmpeqss %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm0, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm0
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; CHECK-NEXT: orps %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_oeq_f32
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; AVX: vcmpeqss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp oeq float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_oeq_f64
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; CHECK: cmpeqsd %xmm1, %xmm0
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; CHECK-NEXT: andpd %xmm0, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm0
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; CHECK-NEXT: orpd %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_oeq_f64
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; AVX: vcmpeqsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp oeq double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_ogt_f32
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; CHECK: cmpltss %xmm0, %xmm1
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; CHECK-NEXT: andps %xmm1, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm1
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; CHECK-NEXT: orps %xmm2, %xmm1
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; AVX-LABEL: select_fcmp_ogt_f32
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; AVX: vcmpltss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp ogt float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_ogt_f64
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; CHECK: cmpltsd %xmm0, %xmm1
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; CHECK-NEXT: andpd %xmm1, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm1
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; CHECK-NEXT: orpd %xmm2, %xmm1
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; AVX-LABEL: select_fcmp_ogt_f64
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; AVX: vcmpltsd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp ogt double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_oge_f32
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; CHECK: cmpless %xmm0, %xmm1
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; CHECK-NEXT: andps %xmm1, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm1
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; CHECK-NEXT: orps %xmm2, %xmm1
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; AVX-LABEL: select_fcmp_oge_f32
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; AVX: vcmpless %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp oge float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_oge_f64
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; CHECK: cmplesd %xmm0, %xmm1
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; CHECK-NEXT: andpd %xmm1, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm1
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; CHECK-NEXT: orpd %xmm2, %xmm1
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; AVX-LABEL: select_fcmp_oge_f64
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; AVX: vcmplesd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp oge double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_olt_f32
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; CHECK: cmpltss %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm0, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm0
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; CHECK-NEXT: orps %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_olt_f32
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; AVX: vcmpltss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp olt float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_olt_f64
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; CHECK: cmpltsd %xmm1, %xmm0
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; CHECK-NEXT: andpd %xmm0, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm0
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; CHECK-NEXT: orpd %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_olt_f64
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; AVX: vcmpltsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp olt double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_ole_f32
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; CHECK: cmpless %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm0, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm0
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; CHECK-NEXT: orps %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_ole_f32
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; AVX: vcmpless %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp ole float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_ole_f64
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; CHECK: cmplesd %xmm1, %xmm0
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; CHECK-NEXT: andpd %xmm0, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm0
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; CHECK-NEXT: orpd %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_ole_f64
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; AVX: vcmplesd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp ole double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_ord_f32
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; CHECK: cmpordss %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm0, %xmm2
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; CHECK-NEXT: andnps %xmm3, %xmm0
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; CHECK-NEXT: orps %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_ord_f32
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; AVX: vcmpordss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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%1 = fcmp ord float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_ord_f64
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; CHECK: cmpordsd %xmm1, %xmm0
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; CHECK-NEXT: andpd %xmm0, %xmm2
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; CHECK-NEXT: andnpd %xmm3, %xmm0
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; CHECK-NEXT: orpd %xmm2, %xmm0
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; AVX-LABEL: select_fcmp_ord_f64
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; AVX: vcmpordsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
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; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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%1 = fcmp ord double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_uno_f32
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; CHECK: cmpunordss %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm0
|
||||
; CHECK-NEXT: orps %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_uno_f32
|
||||
; AVX: vcmpunordss %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp uno float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_uno_f64
|
||||
; CHECK: cmpunordsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: andpd %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm0
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_uno_f64
|
||||
; AVX: vcmpunordsd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp uno double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) {
|
||||
; CHECK-LABEL: select_fcmp_ugt_f32
|
||||
; CHECK: cmpnless %xmm1, %xmm0
|
||||
; CHECK-NEXT: andps %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm0
|
||||
; CHECK-NEXT: orps %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_ugt_f32
|
||||
; AVX: vcmpnless %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ugt float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_ugt_f64
|
||||
; CHECK: cmpnlesd %xmm1, %xmm0
|
||||
; CHECK-NEXT: andpd %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm0
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_ugt_f64
|
||||
; AVX: vcmpnlesd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ugt double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) {
|
||||
; CHECK-LABEL: select_fcmp_uge_f32
|
||||
; CHECK: cmpnltss %xmm1, %xmm0
|
||||
; CHECK-NEXT: andps %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm0
|
||||
; CHECK-NEXT: orps %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_uge_f32
|
||||
; AVX: vcmpnltss %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp uge float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_uge_f64
|
||||
; CHECK: cmpnltsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: andpd %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm0
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_uge_f64
|
||||
; AVX: vcmpnltsd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp uge double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) {
|
||||
; CHECK-LABEL: select_fcmp_ult_f32
|
||||
; CHECK: cmpnless %xmm0, %xmm1
|
||||
; CHECK-NEXT: andps %xmm1, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm1
|
||||
; CHECK-NEXT: orps %xmm2, %xmm1
|
||||
; AVX-LABEL: select_fcmp_ult_f32
|
||||
; AVX: vcmpnless %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ult float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_ult_f64
|
||||
; CHECK: cmpnlesd %xmm0, %xmm1
|
||||
; CHECK-NEXT: andpd %xmm1, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm1
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm1
|
||||
; AVX-LABEL: select_fcmp_ult_f64
|
||||
; AVX: vcmpnlesd %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ult double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) {
|
||||
; CHECK-LABEL: select_fcmp_ule_f32
|
||||
; CHECK: cmpnltss %xmm0, %xmm1
|
||||
; CHECK-NEXT: andps %xmm1, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm1
|
||||
; CHECK-NEXT: orps %xmm2, %xmm1
|
||||
; AVX-LABEL: select_fcmp_ule_f32
|
||||
; AVX: vcmpnltss %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ule float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_ule_f64
|
||||
; CHECK: cmpnltsd %xmm0, %xmm1
|
||||
; CHECK-NEXT: andpd %xmm1, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm1
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm1
|
||||
; AVX-LABEL: select_fcmp_ule_f64
|
||||
; AVX: vcmpnltsd %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp ule double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) {
|
||||
; CHECK-LABEL: select_fcmp_une_f32
|
||||
; CHECK: cmpneqss %xmm1, %xmm0
|
||||
; CHECK-NEXT: andps %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnps %xmm3, %xmm0
|
||||
; CHECK-NEXT: orps %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_une_f32
|
||||
; AVX: vcmpneqss %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandps %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnps %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp une float %a, %b
|
||||
%2 = select i1 %1, float %c, float %d
|
||||
ret float %2
|
||||
}
|
||||
|
||||
define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) {
|
||||
; CHECK-LABEL: select_fcmp_une_f64
|
||||
; CHECK: cmpneqsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: andpd %xmm0, %xmm2
|
||||
; CHECK-NEXT: andnpd %xmm3, %xmm0
|
||||
; CHECK-NEXT: orpd %xmm2, %xmm0
|
||||
; AVX-LABEL: select_fcmp_une_f64
|
||||
; AVX: vcmpneqsd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm1
|
||||
; AVX-NEXT: vandnpd %xmm3, %xmm0, %xmm0
|
||||
; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
||||
%1 = fcmp une double %a, %b
|
||||
%2 = select i1 %1, double %c, double %d
|
||||
ret double %2
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user