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Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation of
live range splitting around loops guided by register pressure. So far, trySplit() simply prints a lot of debug output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121918 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -83,8 +83,8 @@ LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
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void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
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const TargetRegisterInfo *TRI) const {
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OS << '[' << start() << ';' << stop() << ")\t";
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interference()->print(OS, TRI);
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OS << '[' << start() << ';' << stop() << "):";
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TRI->printReg(interference()->reg, OS);
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}
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void LiveIntervalUnion::Query::print(raw_ostream &OS,
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@ -17,6 +17,7 @@
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "SplitKit.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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@ -27,6 +28,7 @@
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineLoopRanges.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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@ -50,9 +52,11 @@ class RAGreedy : public MachineFunctionPass, public RegAllocBase {
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// analyses
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LiveStacks *LS;
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MachineLoopInfo *Loops;
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MachineLoopRanges *LoopRanges;
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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std::auto_ptr<SplitAnalysis> SA;
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public:
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RAGreedy();
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@ -106,6 +110,7 @@ RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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}
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@ -125,6 +130,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreservedID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<MachineLoopRanges>();
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AU.addPreserved<MachineLoopRanges>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(AU);
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@ -256,14 +263,32 @@ unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
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unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
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SmallVectorImpl<LiveInterval*>&SplitVRegs) {
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NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
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DEBUG({
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Order.rewind();
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while (unsigned PhysReg = Order.next()) {
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query(VirtReg, PhysReg).print(dbgs(), TRI);
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for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
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query(VirtReg, *AI).print(dbgs(), TRI);
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SA->analyze(&VirtReg);
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// Get the set of loops that have VirtReg uses and are splittable.
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SplitAnalysis::LoopPtrSet SplitLoops;
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SA->getSplitLoops(SplitLoops);
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Order.rewind();
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while (unsigned PhysReg = Order.next()) {
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for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
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LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
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if (!Q.checkInterference())
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continue;
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LiveIntervalUnion::InterferenceResult IR = Q.firstInterference();
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do {
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DEBUG({dbgs() << " "; IR.print(dbgs(), TRI);});
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for (SplitAnalysis::LoopPtrSet::iterator I = SplitLoops.begin(),
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E = SplitLoops.end(); I != E; ++I) {
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MachineLoopRange *Range = LoopRanges->getLoopRange(*I);
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if (!Range->overlaps(IR.start(), IR.stop()))
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continue;
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DEBUG(dbgs() << ", overlaps " << *Range);
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}
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DEBUG(dbgs() << '\n');
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} while (Q.nextInterference(IR));
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}
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});
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}
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return 0;
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}
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@ -336,9 +361,12 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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Loops = &getAnalysis<MachineLoopInfo>();
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LoopRanges = &getAnalysis<MachineLoopRanges>();
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SA.reset(new SplitAnalysis(*MF, *LIS, *Loops));
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allocatePhysRegs();
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addMBBLiveIns(MF);
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