mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Allow combinations of True/Anti/Output flags for each edge to
support, e.g., dependences on Call instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1009 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
a93bbac606
commit
d0d79c01b4
@ -35,11 +35,16 @@ class SchedGraphNode;
|
|||||||
class SchedGraph;
|
class SchedGraph;
|
||||||
class RegToRefVecMap;
|
class RegToRefVecMap;
|
||||||
class MachineInstr;
|
class MachineInstr;
|
||||||
|
class MachineCodeForBasicBlock;
|
||||||
|
|
||||||
|
|
||||||
/******************** Exported Data Types and Constants ********************/
|
/******************** Exported Data Types and Constants ********************/
|
||||||
|
|
||||||
typedef int ResourceId;
|
typedef int ResourceId;
|
||||||
const ResourceId InvalidResourceId = -1;
|
const ResourceId InvalidRID = -1;
|
||||||
|
const ResourceId MachineCCRegsRID = -2; // use +ve numbers for actual regs
|
||||||
|
const ResourceId MachineIntRegsRID = -3; // use +ve numbers for actual regs
|
||||||
|
const ResourceId MachineFPRegsRID = -4; // use +ve numbers for actual regs
|
||||||
|
|
||||||
|
|
||||||
//*********************** Public Class Declarations ************************/
|
//*********************** Public Class Declarations ************************/
|
||||||
@ -50,14 +55,14 @@ public:
|
|||||||
CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
|
CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
|
||||||
};
|
};
|
||||||
enum DataDepOrderType {
|
enum DataDepOrderType {
|
||||||
TrueDep, AntiDep, OutputDep, NonDataDep
|
TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8
|
||||||
};
|
};
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
SchedGraphNode* src;
|
SchedGraphNode* src;
|
||||||
SchedGraphNode* sink;
|
SchedGraphNode* sink;
|
||||||
SchedGraphEdgeDepType depType;
|
SchedGraphEdgeDepType depType;
|
||||||
DataDepOrderType depOrderType;
|
unsigned int depOrderType;
|
||||||
int minDelay; // cached latency (assumes fixed target arch)
|
int minDelay; // cached latency (assumes fixed target arch)
|
||||||
|
|
||||||
union {
|
union {
|
||||||
@ -73,21 +78,21 @@ public:
|
|||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
SchedGraphEdgeDepType _depType,
|
SchedGraphEdgeDepType _depType,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for explicit def-use or memory def-use edge
|
// constructor for explicit def-use or memory def-use edge
|
||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
const Value* _val,
|
const Value* _val,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for machine register dependence
|
// constructor for machine register dependence
|
||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
unsigned int _regNum,
|
unsigned int _regNum,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for any other machine resource dependences.
|
// constructor for any other machine resource dependences.
|
||||||
@ -306,6 +311,10 @@ private:
|
|||||||
void addMemEdges (const vector<const Instruction*>& memVec,
|
void addMemEdges (const vector<const Instruction*>& memVec,
|
||||||
const TargetMachine& target);
|
const TargetMachine& target);
|
||||||
|
|
||||||
|
void addCallCCEdges (const vector<const Instruction*>& memVec,
|
||||||
|
MachineCodeForBasicBlock& bbMvec,
|
||||||
|
const TargetMachine& target);
|
||||||
|
|
||||||
void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
|
void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
|
||||||
const TargetMachine& target);
|
const TargetMachine& target);
|
||||||
|
|
||||||
|
@ -35,11 +35,16 @@ class SchedGraphNode;
|
|||||||
class SchedGraph;
|
class SchedGraph;
|
||||||
class RegToRefVecMap;
|
class RegToRefVecMap;
|
||||||
class MachineInstr;
|
class MachineInstr;
|
||||||
|
class MachineCodeForBasicBlock;
|
||||||
|
|
||||||
|
|
||||||
/******************** Exported Data Types and Constants ********************/
|
/******************** Exported Data Types and Constants ********************/
|
||||||
|
|
||||||
typedef int ResourceId;
|
typedef int ResourceId;
|
||||||
const ResourceId InvalidResourceId = -1;
|
const ResourceId InvalidRID = -1;
|
||||||
|
const ResourceId MachineCCRegsRID = -2; // use +ve numbers for actual regs
|
||||||
|
const ResourceId MachineIntRegsRID = -3; // use +ve numbers for actual regs
|
||||||
|
const ResourceId MachineFPRegsRID = -4; // use +ve numbers for actual regs
|
||||||
|
|
||||||
|
|
||||||
//*********************** Public Class Declarations ************************/
|
//*********************** Public Class Declarations ************************/
|
||||||
@ -50,14 +55,14 @@ public:
|
|||||||
CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
|
CtrlDep, MemoryDep, DefUseDep, MachineRegister, MachineResource
|
||||||
};
|
};
|
||||||
enum DataDepOrderType {
|
enum DataDepOrderType {
|
||||||
TrueDep, AntiDep, OutputDep, NonDataDep
|
TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8
|
||||||
};
|
};
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
SchedGraphNode* src;
|
SchedGraphNode* src;
|
||||||
SchedGraphNode* sink;
|
SchedGraphNode* sink;
|
||||||
SchedGraphEdgeDepType depType;
|
SchedGraphEdgeDepType depType;
|
||||||
DataDepOrderType depOrderType;
|
unsigned int depOrderType;
|
||||||
int minDelay; // cached latency (assumes fixed target arch)
|
int minDelay; // cached latency (assumes fixed target arch)
|
||||||
|
|
||||||
union {
|
union {
|
||||||
@ -73,21 +78,21 @@ public:
|
|||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
SchedGraphEdgeDepType _depType,
|
SchedGraphEdgeDepType _depType,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for explicit def-use or memory def-use edge
|
// constructor for explicit def-use or memory def-use edge
|
||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
const Value* _val,
|
const Value* _val,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for machine register dependence
|
// constructor for machine register dependence
|
||||||
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
/*ctor*/ SchedGraphEdge(SchedGraphNode* _src,
|
||||||
SchedGraphNode* _sink,
|
SchedGraphNode* _sink,
|
||||||
unsigned int _regNum,
|
unsigned int _regNum,
|
||||||
DataDepOrderType _depOrderType =TrueDep,
|
unsigned int _depOrderType =TrueDep,
|
||||||
int _minDelay = -1);
|
int _minDelay = -1);
|
||||||
|
|
||||||
// constructor for any other machine resource dependences.
|
// constructor for any other machine resource dependences.
|
||||||
@ -306,6 +311,10 @@ private:
|
|||||||
void addMemEdges (const vector<const Instruction*>& memVec,
|
void addMemEdges (const vector<const Instruction*>& memVec,
|
||||||
const TargetMachine& target);
|
const TargetMachine& target);
|
||||||
|
|
||||||
|
void addCallCCEdges (const vector<const Instruction*>& memVec,
|
||||||
|
MachineCodeForBasicBlock& bbMvec,
|
||||||
|
const TargetMachine& target);
|
||||||
|
|
||||||
void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
|
void addMachineRegEdges (RegToRefVecMap& regToRefVecMap,
|
||||||
const TargetMachine& target);
|
const TargetMachine& target);
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user