mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-25 13:24:46 +00:00
[mips] Add NaCl target and forbid indexed loads and stores for it
This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200855 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -390,12 +390,15 @@ let Predicates = [HasStdEnc] in {
|
||||
}
|
||||
|
||||
// Indexed loads and stores.
|
||||
let Predicates = [HasFPIdx, HasStdEnc] in {
|
||||
// Base register + offset register addressing mode (indicated by "x" in the
|
||||
// instruction mnemonic) is disallowed under NaCl.
|
||||
let Predicates = [HasFPIdx, HasStdEnc, IsNotNaCl] in {
|
||||
def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
|
||||
def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
|
||||
}
|
||||
|
||||
let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips] in {
|
||||
let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips,
|
||||
IsNotNaCl] in {
|
||||
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
|
||||
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
|
||||
}
|
||||
@@ -407,7 +410,7 @@ let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
|
||||
}
|
||||
|
||||
// Load/store doubleword indexed unaligned.
|
||||
let Predicates = [NotFP64bit, HasStdEnc] in {
|
||||
let Predicates = [NotFP64bit, HasStdEnc, IsNotNaCl] in {
|
||||
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
|
||||
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
|
||||
}
|
||||
|
@@ -187,6 +187,7 @@ def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
|
||||
AssemblerPredicate<"!FeatureMicroMips">;
|
||||
def IsLE : Predicate<"Subtarget.isLittle()">;
|
||||
def IsBE : Predicate<"!Subtarget.isLittle()">;
|
||||
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
|
||||
|
||||
class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
|
||||
let Predicates = [HasStdEnc];
|
||||
|
@@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
|
||||
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
|
||||
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
|
||||
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
|
||||
RM(_RM), OverrideMode(NoOverride), TM(_TM)
|
||||
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
|
||||
{
|
||||
std::string CPUName = CPU;
|
||||
if (CPUName.empty())
|
||||
|
@@ -125,6 +125,7 @@ protected:
|
||||
|
||||
MipsTargetMachine *TM;
|
||||
|
||||
Triple TargetTriple;
|
||||
public:
|
||||
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
|
||||
AntiDepBreakMode& Mode,
|
||||
@@ -207,6 +208,8 @@ public:
|
||||
|
||||
bool os16() const { return Os16;};
|
||||
|
||||
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
|
||||
|
||||
// for now constant islands are on for the whole compilation unit but we only
|
||||
// really use them if in addition we are in mips16 mode
|
||||
//
|
||||
|
Reference in New Issue
Block a user