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[AArch64] LORID_EL1 register must be treated as read-only

Browse Source 
Patch by: John Brawn

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9105


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235314 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Sukharev 2015-04-20 16:54:37 +00:00
parent ca9313e65e
commit d1e387b9e6
3 changed files with 63 additions and 5 deletions
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8
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
View File

@ -247,7 +247,10 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
{"icc_rpr_el1", ICC_RPR_EL1, 0},
{"ich_vtr_el2", ICH_VTR_EL2, 0},
{"ich_eisr_el2", ICH_EISR_EL2, 0},
{"ich_elsr_el2", ICH_ELSR_EL2, 0}
{"ich_elsr_el2", ICH_ELSR_EL2, 0},
// v8.1a "Limited Ordering Regions" extension-specific system registers
{"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
};
AArch64SysReg::MRSMapper::MRSMapper() {
@ -771,7 +774,6 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings
{"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
{"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
{"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
{"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
// v8.1a "Virtualization host extensions" system registers
{"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps},
@ -804,7 +806,7 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings
};
uint32_t
AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits,
AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits,
bool &Valid) const {
std::string NameLower = Name.lower();

48
test/MC/AArch64/armv8.1a-lor.s
View File

@ -1,4 +1,5 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERROR %s <%t
//------------------------------------------------------------------------------
@ -31,3 +32,48 @@
// CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5]
// CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5]
// CHECK: mrs x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]
ldlarb w0,[w1]
ldlarh x0,[x1]
stllrb w0,[w1]
stllrh x0,[x1]
stllr w0,[w1]
msr LORSA_EL1, #0
msr LOREA_EL1, #0
msr LORN_EL1, #0
msr LORC_EL1, #0
msr LORID_EL1, x0
mrs LORID_EL1, #0
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ldlarb w0,[w1]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ldlarh x0,[x1]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: stllrb w0,[w1]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: stllrh x0,[x1]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: stllr w0,[w1]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: msr LORSA_EL1, #0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: msr LOREA_EL1, #0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: msr LORN_EL1, #0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: msr LORC_EL1, #0
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected writable system register or pstate
// CHECK-ERROR: msr LORID_EL1, x0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: mrs LORID_EL1, #0
// CHECK-ERROR: ^

12
test/MC/Disassembler/AArch64/armv8.1a-lor.txt
View File

@ -20,9 +20,19 @@
0x20,0xa4,0x18,0xd5
0x40,0xa4,0x18,0xd5
0x60,0xa4,0x18,0xd5
0xe0,0xa4,0x38,0xd5
0xe0,0xa4,0x18,0xd5
# CHECK: msr LORSA_EL1, x0
# CHECK: msr LOREA_EL1, x0
# CHECK: msr LORN_EL1, x0
# CHECK: msr LORC_EL1, x0
# CHECK: msr S3_0_C10_C4_7, x0
0x00,0xa4,0x38,0xd5
0x20,0xa4,0x38,0xd5
0x40,0xa4,0x38,0xd5
0x60,0xa4,0x38,0xd5
0xe0,0xa4,0x38,0xd5
# CHECK: mrs x0, LORSA_EL1
# CHECK: mrs x0, LOREA_EL1
# CHECK: mrs x0, LORN_EL1
# CHECK: mrs x0, LORC_EL1
# CHECK: mrs x0, LORID_EL1