[Hexagon] Removing old halfword codegen instructions and updating const32/64 splitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-03-09 20:11:02 +00:00
parent 905c6fb424
commit d2c1ecfc9f
3 changed files with 67 additions and 72 deletions

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@ -4771,30 +4771,29 @@ def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst.h = #HI($label@GOTREL)", "$dst.h = #HI($label@GOTREL)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1,
isAsmParserOnly = 1 in isCodeGenOnly = 1, hasSideEffects = 0 in
def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value), def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.l = #LO($imm_value)", "$dst.h = #HI($global@GOT)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1,
isCodeGenOnly = 1, hasSideEffects = 0 in
def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.l = #LO($global@GOT)",
[]>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1,
isAsmParserOnly = 1 in isCodeGenOnly = 1, hasSideEffects = 0 in
def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value), def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.h = #HI($imm_value)", "$dst.h = #HI($global@GOTREL)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1,
isAsmParserOnly = 1 in isCodeGenOnly = 1, hasSideEffects = 0 in
def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt), def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.l = #LO($jt)", "$dst.l = #LO($global@GOTREL)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isAsmParserOnly = 1 in
def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst.h = #HI($jt)",
[]>;
// This pattern is incorrect. When we add small data, we should change // This pattern is incorrect. When we add small data, we should change
// this pattern to use memw(#foo). // this pattern to use memw(#foo).

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@ -71,6 +71,7 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
return true; return true;
const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
// Loop over all of the basic blocks // Loop over all of the basic blocks
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@ -82,7 +83,19 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
while (MII != MIE) { while (MII != MIE) {
MachineInstr *MI = MII; MachineInstr *MI = MII;
int Opc = MI->getOpcode(); int Opc = MI->getOpcode();
if (Opc == Hexagon::CONST32_set) { if (Opc == Hexagon::CONST32_set_jt) {
int DestReg = MI->getOperand(0).getReg();
MachineOperand &Symbol = MI->getOperand (1);
BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::A2_tfrsi), DestReg).addOperand(Symbol);
// MBB->erase returns the iterator to the next instruction, which is the
// one we want to process next
MII = MBB->erase (MI);
continue;
}
else if (Opc == Hexagon::CONST32_Int_Real &&
MI->getOperand(1).isBlockAddress()) {
int DestReg = MI->getOperand(0).getReg(); int DestReg = MI->getOperand(0).getReg();
MachineOperand &Symbol = MI->getOperand (1); MachineOperand &Symbol = MI->getOperand (1);
@ -95,69 +108,53 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
MII = MBB->erase (MI); MII = MBB->erase (MI);
continue; continue;
} }
else if (Opc == Hexagon::CONST32_set_jt) {
int DestReg = MI->getOperand(0).getReg();
MachineOperand &Symbol = MI->getOperand (1);
BuildMI (*MBB, MII, MI->getDebugLoc(), else if (Opc == Hexagon::CONST32_Int_Real ||
TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol); Opc == Hexagon::CONST32_Float_Real) {
BuildMI (*MBB, MII, MI->getDebugLoc(), int DestReg = MI->getOperand(0).getReg();
TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
// MBB->erase returns the iterator to the next instruction, which is the // We have to convert an FP immediate into its corresponding integer
// one we want to process next // representation
int64_t ImmValue;
if (Opc == Hexagon::CONST32_Float_Real) {
APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
ImmValue = *Val.bitcastToAPInt().getRawData();
}
else
ImmValue = MI->getOperand(1).getImm();
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
MII = MBB->erase (MI); MII = MBB->erase (MI);
continue; continue;
} }
else if (Opc == Hexagon::CONST32_Label) { else if (Opc == Hexagon::CONST64_Int_Real ||
Opc == Hexagon::CONST64_Float_Real) {
int DestReg = MI->getOperand(0).getReg(); int DestReg = MI->getOperand(0).getReg();
MachineOperand &Symbol = MI->getOperand (1);
BuildMI (*MBB, MII, MI->getDebugLoc(), // We have to convert an FP immediate into its corresponding integer
TII->get(Hexagon::LO_PIC), DestReg).addOperand(Symbol); // representation
BuildMI (*MBB, MII, MI->getDebugLoc(), int64_t ImmValue;
TII->get(Hexagon::HI_PIC), DestReg).addOperand(Symbol); if (Opc == Hexagon::CONST64_Float_Real) {
// MBB->erase returns the iterator to the next instruction, which is the APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
// one we want to process next ImmValue = *Val.bitcastToAPInt().getRawData();
MII = MBB->erase (MI); }
continue; else
} ImmValue = MI->getOperand(1).getImm();
else if (Opc == Hexagon::CONST32_Int_Real) {
int DestReg = MI->getOperand(0).getReg();
int64_t ImmValue = MI->getOperand(1).getImm ();
BuildMI (*MBB, MII, MI->getDebugLoc(), unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
TII->get(Hexagon::LOi), DestReg).addImm(ImmValue); unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
MII = MBB->erase (MI);
continue;
}
else if (Opc == Hexagon::CONST64_Int_Real) {
int DestReg = MI->getOperand(0).getReg();
int64_t ImmValue = MI->getOperand(1).getImm ();
unsigned DestLo = Fn.getSubtarget().getRegisterInfo()->getSubReg(
DestReg, Hexagon::subreg_loreg);
unsigned DestHi = Fn.getSubtarget().getRegisterInfo()->getSubReg(
DestReg, Hexagon::subreg_hireg);
int32_t LowWord = (ImmValue & 0xFFFFFFFF); int32_t LowWord = (ImmValue & 0xFFFFFFFF);
int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF; int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
// Lower Registers Lower Half BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::A2_tfrsi), DestLo).addImm(LowWord);
BuildMI (*MBB, MII, MI->getDebugLoc(), BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::LOi), DestLo).addImm(LowWord); TII->get(Hexagon::A2_tfrsi), DestHi).addImm(HighWord);
// Lower Registers Higher Half
BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
// Higher Registers Lower Half
BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
// Higher Registers Higher Half.
BuildMI (*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
MII = MBB->erase (MI); MII = MBB->erase (MI);
continue; continue;
} }
++MII; ++MII;
} }
} }

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@ -76,7 +76,6 @@ char HexagonSplitTFRCondSets::ID = 0;
bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
// Loop over all of the basic blocks. // Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();